Samsung Electronics Co., Ltd.

Hyo-jin Choi

Hak-soo Yu

Jae-Youn Youn

Su-a Kim

Hoi-ju Chung

Mu-jin Seo

Kwang-il Park

Chul-woo Park

Seung-ju Kim

Tae-ho Lee

In Huh

Youn-sik Park

Chang-wook Jeong

Joon-wan Chai

Jeong-hoon Ko

Young-min Oh

Jun-haeng Lee

Hyun-sun Park

Young-Soo Sohn

Sung-Hyun Lee

Dong-Soo Kang

Kyoung-Heon Jeong

Jun-Hee Yoo

A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Device for generating verification vector for circuit design verification, circuit design system, and reinforcement learning method of the device and the circuit design system

A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.

A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.

Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices

In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module.

Memory system for continuously mapping addresses of a memory module having defective locations

A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes first and second sub arrays, the first sub array includes a first set of bank arrays, and the second sub array includes a second set of bank arrays. Each of the upper and lower bank arrays includes first and second portions having different timing parameters with respect to each other. The control logic controls access to the first and second portions such that read/write operation is performed on the first and second portions.

Semiconductor memory device and memory system including the same

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Suwon-si, South Korea

Hyo-jin Choi