Samsung Electronics Co., Ltd.

Hyo-ji Choi

Jae-Won Lee

Jun-youn Kim

Jae-joon Oh

In-jun Hwang

Young-jo Tak

Jae-Kyun Kim

Joo-sung Kim

Jai-kwang Shin

Jong-seob Kim

Young-hwan Park

Woo-chul Jeon

Jong-bong Ha

Ki-yeol Park

Joo-Sung Kim

Young-Jo Tak

Jun-Youn Kim

According to example embodiments a transistor includes a channel layer on a substrate, a first channel supply layer on the channel, a depletion layer, a second channel supply layer, source and drain electrodes on the first channel supply layer, and a gate electrode on the depletion layer. The channel includes a 2DEG channel configured to generate a two-dimensional electron gas and a depletion area. The first channel supply layer corresponds to the 2DEG channel and defines an opening that exposes the depletion area. The depletion layer is on the depletion area of the channel layer. The second channel supply layer is between the depletion layer and the depletion area.

High electron mobility transistor having reduced threshold voltage variation and method of manufacturing the same

Provided are high electron mobility transistors (HEMTs), methods of manufacturing the HEMTs, and electronic devices including the HEMTs. An HEMT may include an impurity containing layer, a partial region of which is selectively activated. The activated region of the impurity containing layer may be used as a depletion forming element. Non-activated regions may be disposed at opposite side of the activated region in the impurity containing layer. A hydrogen content of the activated region may be lower than the hydrogen content of the non-activated region. In another example embodiment, an HEMT may include a depletion forming element that includes a plurality of regions, and properties (e.g., doping concentrations) of the plurality of regions may be changed in a horizontal direction.

High electron mobility transistors, methods of manufacturing the same, and electronic devices including the same

A gallium nitride based semiconductor device includes a silicon-based layer doped simultaneously with boron (B) and germanium (Ge) at a relatively high concentration, a buffer layer on the silicon-based layer, and a nitride stack on the buffer layer. A doping concentration of boron (B) and germanium (Ge) may be higher than 1&#xd7;10/cm.

Gallium nitride based semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device includes forming a silicon substrate, forming a buffer layer on the silicon substrate, and forming a nitride semiconductor layer on the buffer layer. The buffer layer includes a first layer, a second layer, and a third layer. The first layer includes AlInGaN (0&#x2266;x&#x2266;1, 0&#x2266;y&#x2266;1, 0&#x2266;x+y&#x2266;1) and has a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer is formed on the first layer, includes AlInGaN (0&#x2266;x&#x3c;1, 0&#x2266;y&#x3c;1, 0&#x2266;x+y&#x3c;1), and has a lattice constant LP2 that is greater than LP1 and smaller than LP0. The third layer is formed on the second layer, includes AlInGaN (0&#x2266;x&#x3c;1, 0&#x2266;y&#x3c;1, 0&#x2266;x+y&#x3c;1), and has a lattice constant LP3 that is smaller than LP2.

Semiconductor buffer structure, semiconductor device including the same, and method of manufacturing semiconductor device using semiconductor buffer structure

According to example embodiments, a high electron mobility transistor includes: a channel layer including a 2-dimensional electron gas (2DEG); a contact layer on the channel layer; a channel supply layer on the contact layer; a gate electrode on a portion of the channel layer; and source and drain electrodes on at least one of the channel layer, the contact layer, and the channel supply layer. The contact layer is configured to form an ohmic contact on the channel layer. The contact layer is n-type doped and contains a Group III-V compound semiconductor. The source electrode and the drain electrode are spaced apart from opposite sides of the gate electrode.

High electron mobility transistor

A semiconductor buffer structure may include a silicon substrate and a buffer layer that is formed on the silicon substrate. The buffer layer may include a first layer, a second layer formed on the first layer, and a third layer formed on the second layer. The first layer may include AlInGaN (0&#x2266;x&#x2266;1, 0&#x2266;y&#x2266;1, 0&#x2266;x+y&#x2266;1) and have a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer may include AlInGaN (0&#x2266;x&#x3c;1, 0&#x2266;y&#x3c;1, 0&#x2266;x+y&#x3c;1) and have a lattice constant LP2 that is greater than the lattice constant LP1 and smaller than the lattice constant LP0. The third layer may include AlInGaN (0&#x2266;x&#x3c;1, 0&#x2266;y&#x3c;1, 0&#x2266;x+y&#x3c;1) and have a lattice constant LP3 that is greater than the lattice constant LP1 and smaller than the lattice constant LP2.

Multi-layer semiconductor buffer structure, semiconductor device and method of manufacturing the semiconductor device using the multi-layer semiconductor buffer structure

A high electron mobility transistor (HEMT) according to example embodiments includes a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a reverse diode gate structure on the second semiconductor layer. A source and a drain may be on at least one of the first semiconductor layer and the second semiconductor layer. A gate electrode may be on the reverse diode gate structure.

A high electron mobility transistor (HEMT) includes a substrate, an HEMT stack spaced apart from the substrate, and a pseudo-insulation layer (PIL) disposed between the substrate and the HEMT stack. The PIL layer includes at least two materials having different phases. The PIL layer defines an empty space that is wider at an intermediate portion than at an entrance of the empty space.

Growing community of inventors

Seoul, South Korea

Hyo-ji Choi