Samsung Electronics Co., Ltd.

Hyo-dong Ban

Young-hoon Park

Chi-hoon Lee

Hyun-cheol Choe

Eun-young Minn

Chang-sik Choi

Sung-hoon Kho

Se-myeong Jang

Sang-hyun Han

Ho-Ouk Lee

Hoo-Ouk Lee

A semiconductor device includes a substrate partitioned into a cell region, a peripheral circuit region, and an interface region between the cell region and the peripheral circuit region. A guard ring is provided in the interface region of the substrate and surrounds the cell region. A first gate structure is in the cell region, and a second gate structure is in the peripheral circuit region.

Semiconductor devices including guard ring structures

Some embodiments provide a semiconductor substrate having a cell array region and a peripheral circuit region. A plurality of word line patterns are placed in the cell array region, each of which include a word line and a word line capping layer pattern stacked thereon. At least one gate pattern including a gate electrode and a gate capping layer pattern is formed in the peripheral circuit region, the gate capping layer pattern and the word line capping layer pattern having different etching selectivity ratios. A pad interlayer insulating layer and a bit line interlayer insulating layer having approximately the same etching selectivity ratio as the gate capping layer pattern are sequentially formed over a surface of the semiconductor substrate having the gate spacers.

Semiconductor devices having dual capping layer patterns and methods of manufacturing the same

A fuse area structure in a semiconductor device and a method of forming the same are provided. The fuse area structure includes a protection film formed of a passivation film for preventing moisture from seeping into the sidewall of an exposed fuse opening. In order to form the protection film, an etching stop film is formed on a fuse line, and the fuse opening is formed at the same time using the etching stop film when a contact hole required for the semiconductor device is formed. A conductive material layer for forming an upper interconnection layer is formed on the entire surface of a resultant structure on which the contact hole and the fuse opening are formed. The conductive material layer formed on the fuse opening is removed. The exposed etching stop film is removed. Finally, the fuse area is completed by forming a passivation film on the entire surface of the resultant structure and removing the passivation film formed on the bottom of the fuse opening into which laser is to be irradiated. Moisture is effectively prevented from seeping into the interfaces between interlayer dielectric films since the protection film of the passivation film is formed on the sidewall of the fuse opening without an additional process. Also, an additional photolithography process for forming the fuse opening is not necessary since the fuse opening is simultaneously formed when the contact hole is formed.

Fuse area structure including protection film on sidewall of fuse opening in semiconductor device and method of forming the same

An integrated circuit chip having an anti-moisture-absorption film at the edge thereof and a method of forming the anti-moisture-absorption film are provided. In the integrated circuit chip which has predetermined devices inside and whose uppermost layer is covered with a passivation film, a trench is formed by etching interlayer dielectric films to a predetermined depth along the perimeter of the integrated circuit chip to be adjacent to the edge of the integrated circuit chip and an anti-moisture-absorption film is formed to fill the trench or is formed on the sidewall of the trench to a predetermined thickness, in order to prevent moisture from seeping into the edge of the integrated circuit chip. Moisture is effectively prevented from seeping into the edge of the chip by forming the anti-moisture-absorption film at the edge of the chip using the conventional processes of manufacturing the integrated circuit chip without an additional process.

Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film

Method of forming fuse area structure including protection film on sidewall of fuse opening in semiconductor device

A method for manufacturing a semiconductor memory device in which a bit line and a storage electrode of a capacitor are connected to an active area of a semiconductor substrate, respectively, via a contact pad formed in a self-aligning manner. The method includes the steps of forming gate electrodes on the semiconductor substrate, the gate electrodes being covered with a nitride spacer. Then, a thermal oxide layer is formed on the exposed surface of the semiconductor substrate between the gate electrodes. Then, an etch stop layer is formed on the entire surface of the resultant structure having the thermal oxide layer to an appropriate thickness such that the space between the gate electrodes is not buried. Then, a first interlayer dielectric (ILD) film covering the space between the gate electrodes and the top of the gate electrodes is formed, and the first ILD film is then patterned to form a landing pad hole which exposes the spacer and the etch stop layer. Then, the etch stop layer and the thermal oxide layer are removed to expose the surface of the semiconductor substrate, and the landing pad hole is then filled with a conductive material to form landing pads.

Growing community of inventors

Suwon, South Korea

Hyo-dong Ban