Bell Telephone Laboratories

Applied Materials, Inc.

At&t Bell Laboratories

Other

American Telephone and Telegraph, Co.

Hyman J Levinstein

Ashok K Sinha

Shyam P Murarka

Shamouil Shamouilian

Arthur C Adams

Manoocher Birang

Robert W Wu

Cesar D Capio

Vijay D Parkhe

Sasson Roger Somekh

Fusen E Chen

Andreas G Hegedus

John F Cameron

David N Wang

Semyon Sherstinsky

Frederick Vratny

Surinder S Bedi

Arik Donde

Edwin Charles Weldon

Cyril J Mogab

Jon T Clinton

Richard S Wagner

Frank B Alexander, Jr

Jean S Deslauriers

Mei Yin Chang

Zheng Xu

Dan Maydan

Peijun Ding

Ananda H Kumar

Hong Zhang

Hongching Shan

Dennis Stanley Grimard

Gongda Yao

Chan-Lon Yang

Jian Ding

Martin P Lepselter

Robert B Marcus

Gene Y Kohara

Michael G Chafin

Sheila Vaidya

Eliezer Kinsbron

Paul Arleo

Haojiang Li

David S Williams

Louis R Thibault

Roy A Porter

Victor Emerald Hauser, Jr

William R Harshbarger

William E Willenbrock, Jr

William D Powell, Jr

Rudi Hendel

A stand-off pad, and method of fabricating the same, for supporting a workpiece in a spaced apart relation to a workpiece support chuck. More specifically, the wafer stand-off pad is fabricated of a polymeric material, such as polyimide, which is disposed upon the support surface of the chuck. The stand-off pad maintains a wafer, or other workpiece, in a spaced apart relation to the support surface of the chuck. The distance between the underside surface of the wafer and the chuck is defined by the thickness of the stand-off pad. This distance should be larger than the expected diameter of contaminant particles that may lie on the surface of the chuck. In this manner, the contaminant particles do not adhere to the underside of the wafer during processing and the magnitude of the chucking voltage is maintained between the workpiece and the chuck.

Stand-off pad for supporting a wafer on a substrate support chuck

A plasma etch process is described for the etching of oxide with a high selectivity to nitride, including nitride formed on uneven surfaces of a substrate, e.g., on sidewalls of steps on an integrated circuit structure. The addition of a hydrogen-bearing gas to C,F,or C,F,etch gases and a scavenger for fluorine, in a plasma etch process for etching oxide in preference to nitride, results in a high selectivity to nitride which is preserved regardless of the topography of the nitride portions of the substrate surface.

Oxide etch process with high selectivity to nitride suitable for use on surfaces of uneven topography

Titanium is sputtered in an ionized metal plasma sputtering chamber to form titanium silicide in situ in the bottom of openings onto silicon in a series of steps that change the temperature and deposition conditions of sputtering. Ionized titanium is sputtered cold, the temperature is rapidly increased by passing argon through the heated substrate support without sputtering, thereby initiating titanium silicide formation, and then the sputtering of titanium ions is continued at high temperatures to deposit titanium silicide. To deposit titanium silicide in very high aspect ratio openings, a first layer of titanium atoms is sputter deposited in conventional manner to line the sidewalls of the openings, followed by sputtering from a plasma and continuing with the above process.

Method for forming titanium silicide in situ

A puncture resistant electrostatic chuck (20) is described. The chuck (20) comprises at least one electrode (25); and a composite insulator (30) covering the electrode. The composite insulator comprises a matrix material having a conformal holding surface (50) capable of conforming to the substrate (35) under application of an electrostatic force generated by the electrode to reduce leakage of heat transfer fluid held between the substrate and the holding surface. A hard puncture resistant layer, such a layer of fibers or an aromatic polyamide layer, is positioned below the holding surface (50) and is sufficiently hard to increase the puncture resistance of the composite insulator.

Puncture resistant electrostatic chuck

A hybrid Johnsen-Rahbek chuck that provides a combination of both Coulombic and Johnsen-Rahbek chucking mechanisms. More specifically, the chuck contains a plurality of dielectric mesas deposited upon particular regions of the support surface of a chuck. The body of the chuck is generally fabricated from a Johnsen-Rahbek semiconducting dielectric. The mesas are formed from a thin film deposition of a highly-resistive dielectric. Consequently, the thin, highly resistive film prevents excess DC standby current as well as reduces the dependence of the electrostatic chuck performance on the wafer backside morphology and composition.

Hybrid Johnsen-Rahbek electrostatic chuck having highly resistive mesas

A process for fabricating an electrostatic chuck (20) comprising the steps of (c) forming a base (80) having an upper surface with cooling grooves (85) therein, the grooves sized and distributed for holding a coolant therein for cooling the base; and (d) pressure conforming an electrical insulator layer (45) to the grooves on the base by the steps of (i) placing the base into a pressure forming apparatus (25) and applying an electrical insulator layer over the grooves in the base; and (ii) applying a sufficiently high pressure onto the insulator layer to pressure conform the insulator layer to the grooves to form a substantially continuous layer of electrical insulator conformal to the grooves on the base.

Method of making electrostatic chuck with conformal insulator film

An electrostatic chuck (20) for holding a substrate (75) comprises (i) a base (80) having an upper surface (95) with grooves (85) therein, the grooves (85) sized and distributed for holding coolant for cooling a substrate (75), and (ii) a substantially continuous insulator film (45) conformal to the grooves (85) on upper surface (95) of the base (80). The base (80) can be electrically conductive and capable of serving as the electrode (50) of the chuck (20), or the electrode (50) can be embedded in the insulator film (45). The insulator film (45) has a dielectric breakdown strength sufficiently high that when a substrate (75) placed on the chuck (20) and electrically biased with respect to the electrode (50), electrostatic charge accumulates in the substrate (75) and in the electrode (50) forming an electrostatic force that attracts and holds the substrate (75) to the chuck (20). Preferably the chuck (20) is fabricated using a pressure forming process, and more preferably using a pressure differential process.

Electrostatic chuck with conformal insulator film

A plasma etch reactor and a related method of its operation to provide self-cleaning of its top electrode, which is subject to being coated by polymer deposits during normal operation. In one form of the invention, radio-frequency (rf) power is applied to the top electrode on a continuous basis, but at a much lower power level than that of a primary rf power source used to supply power through a lower electrode, to generate and sustain a plasma in the reactor. The small rf power applied through the top electrode is selected to be of such a level as to remove deposits from the electrode continuously, as they are formed, but without removing any significant amount of electrode material. In another form of the invention, power is applied to the top electrode periodically during cleaning periods and power supply to the lower electrode is suspended during the cleaning periods. The two cleaning approaches may also be combined, with continuous cleaning being supplemented with occasional or periodic dry cleaning while etch processing is suspended.

Self-cleaning polymer-free top electrode for parallel electrode etch

The invention is embodied in a method of determining an optimum de-chucking voltage for nullifying residual electrostatic forces on a wafer in an electrostatic chuck for removal of the wafer from the chuck, including holding the wafer on the electrostatic chuck by applying an electrostatic potential to the chuck, introducing a gas between the wafer and the chuck, reducing the electrostatic potential of the chuck while observing a rate of leakage of the gas from between the wafer and the chuck, and recording as the optimum dechucking voltage the value of the electrostatic potential obtaining when the rate of leakage exceeds a predetermined threshold.

Method of determining a dechucking voltage which nullifies a residual

Submicron vias are filled by sputter deposition of a conductor such as aluminum onto a substrate such as silicon or silicon oxides. The deposited aluminum film is deposited at a first lower temperature and then the temperature is increased. The differential coefficient of thermal expansion of the substrate relative to the metal conductor forces the conductor to expand into the via. Maintaining an effective thickness and controlling the temperature increase from the first temperature to the second temperature, effectively and reliably fills submicron vias having aspect ratios up to 4. The present invention is particularly useful with filling vias having re-entrant angles of up to 20.degree..

Method for planarization of submicron vias and the manufacture of

Insulation between first and second levels of aluminum metallization in semiconductor integrated circuit structures comprises a plasma planarized, deposited silicon dioxide layer and another silicon dioxide layer deposited upon said plasma planarized layer.

Multiple insulating layer for two-level interconnected metallization in

A method for fabricating a device which includes a tantalum silicide structure, and which is essentially free of conductive etch residues, is disclosed. The method includes the steps of depositing tantalum and silicon onto a substrate, patterning the tantalum and silicon, and then sintering the patterned tantalum and silicon to form a patterned layer of tantalum silicide.

Devices having tantalum silicide structures

For optimal performance, the threshold voltages V.sub.TP and V.sub.TN of the p- and n-channel transistors in a CMOS device should be the respective complements of each other. In polysilicon-gate devices, this can be achieved by adjusting the corresponding gate-metal work function utilizing p.sup.+ and n.sup.+ polysilicon for the respective gates of the p- and n-channel transistors. However, when a refractory metal silicide-over-polysilicon gate structure is employed in a VLSI CMOS device in which the gates of a pair of adjacent complementary transistors are connected together, an anomalously large negative V.sub.TP is measured. The invention is a unique process sequence that achieves substantially complementary p- and n-channel transistor thresholds in a high-speed VLSI CMOS device that includes silicide-over-polysilicon gates.

Method of fabricating VLSI CMOS devices having complementary threshold

It has been found that stress in X-ray transparent films used to form masks for X-ray lithography also cause distortions of the film and of the high-resolution X-ray-absorptive pattern formed thereon. A method is disclosed which anneals boron nitride films for use in X-ray masks in such a way as to control stress.

Boron nitride X-ray masks with controlled stress

Growing community of inventors

Berkeley Heights, NJ, United States of America

Hyman J Levinstein