Samsung Electronics Co., Ltd.

Hyeonwu Kim

Kyungbo Yang

Dongik Jeon

Seokwon Ahn

Seok-Won Ahn

Changkyu Seol

Yongwon Cho

Younggeon Yoo

Chanho Yoon

Jae Hun Jang

Hyungjoon Park

Daekyoung Kim

Hyeongseok Song

Youngho Gong

Soonsuk Hwang

Hojun Jo

Jihwan Mun

Yoonjin Lee

Example embodiments are directed to a method for programming a storage device including a nonvolatile memory device and a storage controller for storing multi-bit data, programming, by the storage controller, the multi-bit data into the nonvolatile memory device based on a pre-programming operation, reading state group data of the multi-bit data generated in the nonvolatile memory device based on a program result of the pre-programming operation, and performing, by the storage controller, error correction decoding on the state group data.

Storage device for backing up state group data in the event of a sudden power-off and program method thereof

A method of operating a storage device that includes a nonvolatile memory device and a controller that controls an operation of the nonvolatile memory device includes issuing, by the controller, a first command to the nonvolatile memory device, reading, by the nonvolatile memory device, first data from a memory cell array into a page buffer of the nonvolatile memory device, in response to the first command, issuing, by the controller, a second command to the nonvolatile memory device, and outputting, by the nonvolatile memory device to the controller, in response to the second command, status information indicating whether a read operation according to the first command has been completed and second data obtained from the page buffer of the nonvolatile memory device.

Storage device and operating method thereof that outputs status information and read data together

A memory controller receives a write request and write data from a host, stores first entry information including a write buffer pointer indicating a location where the write data is temporarily stored in a write buffer and a first logical address corresponding to the write request in an entry buffer, stores an entry index generated based on the first entry information in a first storage space corresponding to the first logical address in a logical-to-physical (L2P) mapping information storage circuit, and updates the entry index stored in the first storage space to a physical address newly mapped to the first logical address as the write data is programmed in a memory device.

Memory controller with improved mapping information management, memory system including the same, and operating method of memory controller

A storage device may include a non-volatile memory including a plurality of zones, the non-volatile memory configured to sequentially store data in at least one of the plurality of zones, and a processing circuitry configured to, receive a first write command and first data from a host, the first write command including a first logical address, identify a first zone of the plurality of zones based on the first logical address, compress the first data based on compression settings corresponding to the first zone, and write the compressed first data to the first zone.

Storage device and operating method thereof including a plurality of zones and operating method thereof

Storage device including a plurality of zones having separate compression ratios and operating method thereof

A storage device includes a first memory device including a plurality of first memory cells, a second memory device including a plurality of second memory cells having the same type as the plurality of first memory cells, and a controller that communicates with the first memory device through a first memory interface and communicates with the second memory device through a second memory interface having an operating speed higher than an operating speed of the first memory interface.

Storage device having a controller that communicates with each of two memories through separate interfaces

Storage device and operating method thereof

A method of operating a controller which controls a nonvolatile memory device includes enabling a command latch enable signal, an address latch enable signal, and a write enable signal and transmitting multiple data signals including a command and an address to the nonvolatile memory device in synchronization with the enabled write enable signal. A number of DQ lines through which the plurality of data signals are transmitted is greater than a number of bits of each of the data signals. The method also include disabling the command latch enable signal after the command is transmitted, and disabling the address latch enable signal and the write enable signal after the address is transmitted.

Storage device having wide input/output and method of operating the same

A storage device includes a controller and a memory. In response to a request of a host, the controller generates: (A) a first list as a result of counting: (1) the number of first page numbers included in a first range among page numbers included in a logical address received from the host and (2) the number of second page numbers included in a second range not overlapping the first range, (B) generates a second list as a result of respectively grouping the first page numbers and the second page numbers based on the first list, and (C) translates the logical address to a physical address based on the second list and the first map data. The memory stores the first map data to be provided to the controller. The first map data matches the first page numbers and the second page numbers with respective physical addresses.

Storage device for performing map scheduling and electronic device including the same

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Gyeongsangbuk0do, South Korea

Hyeonwu Kim