Samsung Electronics Co., Ltd.

Sungkyunkwan University

Ulsan National Institute of Science and Technology

Seoul National University

Harvard College

Cornell University

The University of Chicago

Unist (ulsan National Institute of Science and Technology )

Research & Business Foundation Sungyunkwan University

Unist, Inc.

Hyeonjin Shin

Seongjun Park

Yeonchoo Cho

Minsu Seol

Keunwook Shin

Kyung-Eun Byun

Changseok Lee

Hyunjae Song

Sangwon Kim

Minhyun Lee

Jaeho Lee

Haeryong Kim

Seunggeol Nam

Eunkyu Lee

Sanghyun Jo

Changhyun Kim

Dongwook Lee

Jinseong Heo

Yunseong Lee

Sangwoo Kim

Sanghun Lee

Jae-Young Kim

Kiyoung Lee

Donhee Ham

Taejin Choi

Taejin Park

Soyoung Lee

Yonghoon Kim

Jaeyoung Kim

Hyoyoung Lee

Seungwon Lee

Jaewon Lee

Junsoo Kim

Jisoo Kyoung

Janghee Lee

Jihye Kim

Minsu Kim

Hyun Soo Park

Sang-Woo Kim

Sang-woo Kim

Woojin Lee

Jaeman Choi

Sanghoon Ahn

Jaeyoung Choi

Taewoo Kim

Jeongho Cho

Ki-bum Kim

Hanjin Lim

Soomin Kim

Hyangsook Lee

Hansu Kim

Moonseok Kwon

Sangyeon Han

Seonmi Yoon

Alum Jung

Kyungeun Byun

Hyeonsuk Shin

Seongjun Jeong

Minseok Yoo

Seokmo Hong

Junyoung Kwon

Kibum Kim

Houk Jang

Hyunseok Lim

Hyoungsub Kim

Jaehwan Jung

Wonsik Ahn

Mirine Leem

Jeongmin Baik

Byeonguk Ye

Van Luan Nguyen

Hoijoon Kim

Jiwoong Park

Saien Xie

Henry Julian Hinton

Kyungyeol Ma

Ahrum Sohn

Huijung Kim

Jeonil Lee

Hyejin Cho

Ho Won Jang

Eunbi Cho

Junghoo Shin

Seongsu Kim

Sungjoo An

Jinsung Chun

Yunho Kang

Taehyeong Kim

Youngtek Oh

Jongmyeong Lee

Younghee Lee

Minwoo Kwon

Kaoru Yamamoto

Heejun Yang

Eunsung Kim

Han Joong Kim

Minseok Shin

Donghyun Im

Hyungseok Kang

An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of the rest region of the semiconductor layer, a metal layer facing the semiconductor layer, a semi-metal layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the semi-metal layer and the semiconductor and covering the first region.

Interconnect structure to reduce contact resistance, electronic device including the same, and method of manufacturing the interconnect structure

Disclosed is a nanocrystalline boron nitride film having a relatively low dielectric constant and excellent mechanical properties. The nanocrystalline boron nitride film includes a crystalline boron nitride compound, and has a dielectric constant within a range of 2.5 to 5.5 at a 100 kHz operating frequency.

Nanocrystalline boron nitride film, image sensor including the same, field effect transistor including the same, and method of fabricating the nanocrystalline boron nitride film

Provided are soluble graphene quantum dots and light-emitting devices including the same. The soluble graphene quantum dot has an anthracenyl N-alkyl maleimide functional group at an edge thereof, thereby exhibiting improved solubility and/or improved emission characteristics.

Soluble graphene quantum dots and light-emitting device using the same

Provided are nanocrystalline graphene and a method of forming the same. The nanocrystalline graphene may include a plurality of grains formed by stacking a plurality of graphene sheets and has a grain density of about 500 ea/μmor higher and a root-mean-square (RMS) roughness in a range of about 0.1 or more to about 1.0 or less. When the nanocrystalline graphene has a grain density and a RMS roughness with these ranges, nanocrystalline graphene capable of covering the entirety of a large area on a substrate as a thin layer may be provided.

Nanocrystalline graphene and method of forming nanocrystalline graphene

Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

Semiconductor device including two-dimensional semiconductor material

An electronic device including a two-dimensional material is provided. The electronic device may include a substrate; a metal layer on a partial region of the substrate; a two-dimensional material layer over the metal layer and an upper surface of the substrate; and an insertion layer between the metal layer and the two-dimensional material layer.

Electronic device including two-dimensional material and method of manufacturing the same

Provided are an interconnect structure and an electronic device including the same. The interconnect structure may include a conductive wiring having a certain pattern, a dielectric layer on side surfaces of the conductive wiring, a capping layer on the conductive wiring, and a graphene layer on the dielectric layer. The graphene layer may include a graphene material. A ratio of carbons having spbonds to carbons having spbonds in the graphene material is 1 or less.

Interconnect structure and electronic device including the same

Provided are a wiring including a graphene layer and a method of manufacturing the wiring. The method may include growing a graphene layer on a substrate and doping the graphene layer with a metal. The graphene layer may be grown using a plasma of a hydrocarbon at a temperature of about 200° C. to about 600° C. by plasma enhanced chemical vapor deposition (PECVD).

Wiring including graphene layer and method of manufacturing the same

A method of calculating a thickness of a graphene layer and a method of measuring a content of silicon carbide, by using X-ray photoelectron spectroscopy (XPS), are provided. The method of calculating the thickness of the graphene layer, which is directly grown on a silicon substrate, includes measuring the thickness of the graphene layer directly grown on the silicon substrate, by using a ratio between a signal intensity of a photoelectron beam emitted from the graphene layer and a signal intensity of a photoelectron beam emitted from the silicon substrate.

Method of calculating thickness of graphene layer and method of measuring content of silicon carbide by using XPS

Disclosed are a field effect transistor and a method of manufacturing the same. The field effect transistor includes a source electrode on a substrate, a drain electrode separated from the source electrode, and channels connected between the source electrode and the drain electrode, gate insulating layers, and a gate electrode. The channels may have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate. The gate insulating layers may be in the channels. The gate electrode may be insulated from the source electrode and the drain electrode by the gate insulating layers.

Field effect transistor including channels having a hollow closed cross-sectional structure and method of manufacturing the same

Disclosed are an interconnect structure, an electronic device including the same, and a method of manufacturing the interconnect structure. The interconnect structure includes a dielectric layer; a conductive interconnect on the dielectric layer; and a graphene cap layer on the conductive interconnect. The graphene cap layer contains graphene quantum dots, has a carbon content of 80 at % or more, and has an oxygen content of 15 at % or less.

Interconnect structure, electronic device including the same, and method of manufacturing interconnect structure

Disclosed are an electronic device including a two-dimensional material, and a method of fabricating the electronic device. The electronic device may include a first metal layer including a transition metal, a second metal layer on the first metal layer and including gold (Au), and a two-dimensional material layer between the first metal layer and the second metal layer. The two-dimensional material layer may include a transition metal dichalcogenide (TMD). The two-dimensional material layer may be formed as a chalcogen element diffuses into the second metal layer and reacts with the transition metal of the first metal layer adjacent to the second metal layer.

Electronic device including two-dimensional material and method of fabricating the same

A method of forming a material film includes providing a non-photosensitive mask on a substrate to expose a partial region of the substrate, forming a material film on the partial region of the substrate using a sputtering process, removing the non-photosensitive mask, and heat-treating the substrate and the material film from which the non-photosensitive mask is removed under a first gas atmosphere. The material film includes a transition metal and a chalcogen element. The sputtering process may include an RF magnetron sputtering process. The heat treatment may be performed at a higher temperature than a temperature of the forming the material film.

Method of forming material layer

Provided are a metal chalcogenide thin film and a method and device for manufacturing the same. The metal chalcogenide thin film includes a transition metal element and a chalcogen element, and at least one of the transition metal element and the chalcogen element having a composition gradient along the surface of the metal chalcogenide thin film, the composition gradient being an in-plane composition gradient. The metal chalcogenide thin film may be prepared by using a manufacturing method including providing a transition metal precursor and a chalcogen precursor on a substrate by using a confined reaction space in such a manner that at least one of the transition metal precursor and the chalcogen precursor forms a concentration gradient according to a position on the surface of the substrate; and heat-treating the substrate.

Metal chalcogenide film and method and device for manufacturing the same

Provided is a vertical nonvolatile memory device in which a thickness of one memory cell is reduced to reduce an entire thickness of a memory cell string and increase the number of stacked memory cells. The nonvolatile memory device includes a plurality of memory cell strings. Each of the memory cell strings may include a plurality of insulating spacers each extending in a first direction, a plurality of gate electrodes each extending in the first direction and alternately arranged with the plurality of insulating spacers in a second direction perpendicular to the first direction, and a plurality of contacts respectively arranged to contact a side surface of the plurality of gate electrodes respectively corresponding to the plurality of contacts.

Vertical nonvolatile memory device including memory cell string

Growing community of inventors

Suwon-si, South Korea

Hyeonjin Shin