Industry-university Cooperation Foundation Hanyang University

Samsung Electronics Co., Ltd.

Hyeongmin Seo

Jaeduk Han

Hyuntae Kim

Sanghun Lee

Eunji Song

YunSeong Jo

Jeonghyu Yang

Dongho Choi

Kwanghee Choi

Youngho Kwak

Yongho Song

Dongju Yang

Gaeryun Sung

According to an aspect, a data inversion circuit configured to perform DBI-DC encoding using a PAM 4 signal may comprise a data generation unit configured to generate input data based on the PAM 4 signal and a data transmission unit comprising, an auxiliary signal generation unit configured to generate an auxiliary signal that determines whether to perform encoding on the input data by analyzing a plurality of data symbols included in the input data, a channel comprising a plurality of data lines and a data encoding unit configured to generate encoded data by performing DBI (data bus inversion) encoding on the data based on the auxiliary signal and to transmit the generated encoded data to a data reception unit via the channel.

Data inversion circuit to perform DBI-DC encoding using PAM 4 signal

A clock data recovery circuit includes a phase-locked loop configured to generate a plurality of clock signals having unequal phases relative to each other, in response to a received clock signal, and a phase interpolator configured to interpolate phases of the plurality of clock signals during generation of multiphase sampling clock signals. A sampling clock adjustment circuit is also provided, which is configured to generate a plurality of data symbols by sampling a received data signal at sampling time points of the multiphase sampling clock signals, and further configured to: detect, from the plurality of data symbols, a first data pattern set to have a transition point immediately before a first reference data symbol, and a second data pattern set to have a transition point immediately after a second reference data symbol, detect a first signal level of the first data pattern at a sampling time point for sampling the first reference data symbol, detect a second signal level of the second data pattern at a sampling time point for sampling the second reference data symbol, and adjust phases of the multiphase sampling clock signals according to a result of comparing the first signal level to the second signal level.

Clock data recovery circuits and electronic systems that support data-based clock recovery

According to an aspect, a data inversion circuit configured to perform DBI-AC encoding using a PAM 4 signal may comprise a data generation unit configured to generate input data based on the PAM 4 signal, a channel comprising N data lines, a first auxiliary signal generation unit configured to generate a first auxiliary signal that determines whether to perform a first encoding on the input data based on the number of each of a plurality of data symbols included in the input data, a first data encoding unit configured to generate intermediate data by performing the first encoding on the input data based on the first auxiliary signal, a second auxiliary signal generation unit configured to generate a second auxiliary signal that determines whether to perform a third encoding on the intermediate data by analyzing the relationship between a plurality of data symbols at a current time point and a plurality of data symbols at a previous time point included in the intermediate data and a second data encoding unit configured to generate encoded data by performing the third encoding on the intermediate data based on the second auxiliary signal, and to transmit the generated encoded data to a data reception unit via the channel and the first auxiliary signal and the second auxiliary signal may be combined into one signal and implemented as a PAM 4 signal.

Data inversion circuit to perform DBI-AC encoding using PAM 4 signal

A high-speed 4:1 multiplexer according to an embodiment comprises an input circuit unit including a first circuit that receives a first data as an input signal, and outputs a first output data as an output signal, a second circuit that receives a second data as an input signal, and outputs a second output data as an output signal, a third circuit that receives a third data as an input signal, and outputs a third output data as an output signal, and a fourth circuit that receives a fourth data as an input signal, and outputs a fourth output data as an output signal, a first stage for dividing the output data of the input circuit unit by two and receiving as an input signal, and outputting a first intermediate data and a second intermediate data as an output signal and a second stage of receiving the first intermediate data and the second intermediate data as an input signal and outputting a final data as an output signal.

High speed 4:1 multiplexer

Growing community of inventors

Seoul, South Korea

Hyeongmin Seo