Skhynix Inc.

Hyeong Soo Jeong

Dong Beom Lee

Hyun Seung Kim

Mino Kim

Seung Hun Lee

Geun Ho Choi

Tae Kyun Shin

Gang Sik Lee

Young Bo Shim

Eun Je Kim

A semiconductor device includes first and second memory devices configured to share a first transmission line from which a write clock is received and a second transmission line from which data is received. The memory devices receive the data through first to eighth internal clocks that are generated by dividing a frequency of the write clock, and selectively align and store at least some of the data that is received in synchronization with the first to eighth internal clocks based on timing at which the data is synchronized with the write clock.

Semiconductor system for performing a data alignment operation

An electronic device may include: a control pulse generation circuit configured to selectively generate one of a first control pulse and a second control pulse on the basis of a reference code during a test period; and a voltage control code generation circuit configured to perform an addition operation or subtraction operation on a logic bit set of a voltage control code to set the voltage level of an operation voltage on the basis of the first and second control pulses.

Electronic device and electronic system for generating an operation voltage

A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates an operation code and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on the operation code and the strobe pulse and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys based on a plurality of operation codes and the strobe pulse and prevents the generation of the enable signal for a predetermined time when the plurality of guard keys are not sequentially enabled.

Enable signal generation circuit and semiconductor apparatus using the same

A semiconductor device includes a flag generation circuit configured to receive region fuse data and used fuse data which are generated from a fuse set selected based on a fuse set selection signal among from fuse sets and generate a bank resource flag to control a repair operation for a bank on which a repair operation has not been performed, based on the region fuse data and the used fuse data. The semiconductor device also includes a repair control circuit configured to control the repair operation for banks sharing the fuse sets based on the bank resource flag.

Semiconductor devices for controlling repair operations

An apparatus includes a selection data generation circuit configured to generate selection data from fuse data or generate the selection data having a preset test input pattern, depending on whether a failure test is entered; and a failure flag generation circuit configured to generate latch data by latching the selection data, and generate a failure flag by detecting whether the latch data has a preset test pattern.

Apparatus configured to perform a test operation

A memory device includes a data storage circuit configured to store, when a write operation is performed, a first internal write data and a second internal write data in a memory cell array which is accessed by an internal address, and output, when a read operation is performed, data stored in a memory cell array which is accessed by the internal address, as internal read data; and a flag generation circuit configured to generate a flag for controlling generation of a data strobe signal, based on the internal read data.

Memory device and memory system controlling generation of data strobe signal based on executing a test

An apparatus includes a boot-up control circuit configured to, when a first boot-up operation is performed, latch first fuse data by receiving the first fuse data and fuse information from a fuse circuit and configured to, when a second boot-up operation is performed, latch second fuse data by receiving the second fuse data from the fuse circuit based on the fuse information; and a rupture control circuit configured to store a failure address as the second fuse data by rupturing the fuse circuit based on the fuse information.

Apparatus performing repair operation

A semiconductor apparatus includes a fuse array, storage circuit, parity circuit, fuse data register, parity data register, and error correction circuit. The fuse array stores information about fail addresses and outputs the stored information as fuse data during a boot-up operation. Wherein, the storage circuit stores the fuse data and outputs it as a storage signal and the parity circuit performs a parity operation based on the storage signal and outputs a result of the parity operation as a parity signal, the fuse data register receives and stores the fuse data and outputs the stored data as a fuse register output signal. The parity data register receives and stores the parity signal and outputs the stored information as a parity register output signal, the error correction circuit corrects an error of the fuse register output signal based on the parity register output signal and outputs the error-corrected signal as repair information.

Semiconductor apparatus

A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates a plurality of operation codes and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on at least a part of an operation code, among the plurality of operation codes, and the strobe pulse, and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys, after the seed signal is generated, based on the plurality of operation codes and the strobe pulse, and prevents the generation of the enable signal when any one of the plurality of guard keys is disabled.

A training device may include a pattern generation circuit configured to generate a pattern signal in response to a read command, a delay calculation circuit configured to calculate a delay amount based on comparison results between a generation timing of the pattern signal and generation timings of pattern signals which are generated from one or more other training devices and transmitted to a corresponding training device, and a delay adjusting circuit configured to adjust a delay of a DQ signal in a chip including the corresponding training device, based on the delay amount.

Training device and semiconductor system including the same

An electrical fuse (E-fuse) circuit is disclosed, which relates to a technology for processing a failed part of the E-fuse circuit. The E-fuse circuit comprising: a boot-up controller configured to generate at least one fuse address and a sensing enable signal, an electrical fuse (E-fuse) array configured to include a plurality of fuse sets, and configured to output fuse data including failed data if a failure has occurred in an E-fuse of the plurality of fuse sets, based on the fuse address and the sensing enable signal, a fail controller configured to detect failed data from the fuse data, and output a failed signal and a failed address storage circuit configured to store a failed address from among the fuse addresses based on the failed signal.

E-fuse circuit

A semiconductor device includes an internal command generation circuit suitable for generating a first internal command, a second internal command, and a third internal command based on a command/address signal. The semiconductor device also includes a driving signal generation circuit suitable for enabling a fuse driving signal for reading fuse data from a nonvolatile memory circuit, where the fuse signal is enabled while the second internal command is inputted a predetermined number of times. Further included is an output circuit suitable for outputting the fuse data in response to the third internal command.

Growing community of inventors

Icheon-si, South Korea

Hyeong Soo Jeong