Samsung Electronics Co., Ltd.

Hyeong-jun Kim

Chang-Wook Jeong

Jae-Hyun Park

Won-Cheol Jeong

Gi-Tae Jeong

Seung-Pil Ko

Sun-Pil Youn

Dae-Hwan Kang

Dong-Won Lim

Jeong Chang-Wook

Jin-Tae Kang

Young-Jae Joo

Jae-Min Shin

Jung-Hoon Park

Myoung-jae Lee

In-gyu Baek

Seung-eon Ahn

Jang-Eun Lee

Se-Ho Lee

Jae-Hee Oh

Dae-Won Ha

Kyung-Chang Ryoo

Dong-Chul Kim

Sun-Ae Seo

Hong-Sik Jeong

Eun-Kyung Yim

Min-ji Kim

Jung-hyuk Lee

Yong-keun Jee

Hyeong-hwan Choi

Jong-soon Kim

Hyeong-Hwan Choi

Jong-Soon Kim

A robot cleaner is disclosed. The robot cleaner includes an infrared sensor including a light emitting device configured to output an infrared ray to a floor and a light receiving device configured to receive the infrared ray reflected from the floor and convert the received infrared ray into an electric signal and output the electric signal; and a processor configured to determine an output voltage of the electrical signal if the electrical signal is received from the infrared sensor, control a travel direction of the robot cleaner based on the output voltage and a predetermined first threshold voltage, and control a suction mode of the robot cleaner based on the output voltage and a predetermined second threshold voltage, wherein the second threshold voltage is higher than the first threshold voltage.

Robot cleaner and control method thereof

Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper bit line.

Resistive memory device

A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.

Multiple level cell phase-change memory devices having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices

A phase-change random-access memory (PRAM) device includes a chalcogenide element, the chalcogenide element comprising a material which can assume a crystalline state or an amorphous state upon application of a heating current. A first contact is connected to a first region of the chalcogenide element and has a first cross-sectional area. A second contact is connected to a second region of the chalcogenide element and having a second cross-sectional area. A first programmable volume of the chalcogenide material is defined in the first region of the chalcogenide element, a state of the first programmable volume being programmable according to a resistance associated with the first contact. A second programmable volume of the chalcogenide material is defined in the second region of the chalcogenide element, a state of the second programmable volume being programmable according to a second resistance associated with the second contact.

Multi-bit phase-change random access memory (PRAM) with diameter-controlled contacts and methods of fabricating and programming the same

A phase change memory device and a write method thereof allow writing of both volatile and non-volatile data on the phase change memory device. The phase change memory device may be written by setting a write mode as one of a volatile write mode and a non-volatile write mode, and writing data as volatile or non-volatile by applying a write pulse corresponding to the write mode, wherein, when power is not supplied to the phase change memory device, the non-volatile data is retained and the volatile data is not retained.

Phase change memory device and write method thereof

Multiple level cell phase-change memory device having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices

A multi-bit memory cell stores information corresponding to a high resistive state and multiple other resistive states lower than the high resistive state. A resistance of a memory element within the multi-bit memory cell switches from the high resistive state to one of the other multiple resistive states by applying a corresponding current to the memory element.

Multi-state resistive memory element, multi-bit resistive memory cell, operating method thereof, and data processing system using the memory element

In a memory device and in a method of programming the same, a memory device comprises: a plurality of memory cells, each memory cell comprising a resistance-changeable material that has an initial resistance that is determined in response to an applied programming current in a programming operation; and a modification circuit that modifies the resistance of the memory cell following a programming operation of the memory cell to vary the resistance of the memory cell from the initial resistance to a second resistance by applying a saturation current in a saturation operation. Each memory cell is connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation, that is used to apply the saturation current to the corresponding memory cell in the saturation operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a subsequent read operation.

Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices

A non-volatile memory device which can be highly-integrated without a decrease in reliability, and a method of fabricating the same, are provided. In the non-volatile memory device, a first doped layer of a first conductivity type is disposed on a substrate. A semiconductor pillar of a second conductivity type opposite to the first conductivity type extends upward from the first doped layer. A first control gate electrode substantially surrounds a first sidewall of the semiconductor pillar. A second control gate electrode substantially surrounds a second sidewall of the semiconductor pillar and is separated from the first control gate electrode. A second doped layer of the first conductivity type is disposed on the semiconductor pillar.

Non-volatile memory device and semiconductor package including the same

Methods of forming integrated circuit devices include forming at least one non-volatile memory cell on a substrate. The memory cell includes a plurality of phase-changeable material regions therein that are electrically coupled in series. This plurality of phase-changeable material regions are collectively configured to support at least 2-bits of data when serially programmed using at least four serial program currents. Each of the plurality of phase-changeable material regions has different electrical resistance characteristics when programmed.

Methods of fabricating multi-bit phase-change memory devices and devices formed thereby

In a method of controlling resistance drift in a memory cell of a resistance-changeable material memory device, the resistance changeable material in the memory cell is treated so that a drift parameter for the memory cell is less than about 0.18, wherein a change in resistance of a memory cell over the time period is determined according to the relationship:;where Rrepresents a final resistance of the memory cell following the time period, Rrepresents the initial resistance of the memory cell following the programming operation, t represents the time period; and &#x3b1; represents the drift parameter.

Multiple level cell phase-change memory devices having controlled resistance drift parameter, memory systems employing such devices and methods of reading memory devices

Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

Magnetic random access memory cells having split subdigit lines having cladding layers thereon and methods of fabricating the same

Phase change memory devices and methods of making phase changeable memory devices including a heating electrode disposed on a substrate are provided. The heating electrode includes an electrode hole in the heating electrode. A phase change material pattern is provided in the electrode hole and contacts a sidewall of the electrode hole. In some embodiments, the electrode hole extends through the heating electrode. In some embodiments, the phase changeable material pattern only contacts the electrode at a sidewall of the electrode hole.

Phase change memory devices with contact surface area to a phase changeable material defined by a sidewall of an electrode hole and methods of forming the same

Phase change Random Access Memory (PRAM) devices include a substrate and a phase change layer pattern on the substrate. The phase change layer pattern includes a sharp tip and at least one wall that extends from the sharp tip in a direction away from the substrate. At least one contact hole node is provided that contacts the phase change material pattern adjacent the sharp tip.

Memory devices having sharp-tipped phase change layer patterns

A magnetic random access memory device may include a first electrode on a substrate, a magnetic tunneling junction element electrically connected to the electrode, and a second electrode electrically connected to the first electrode through the magnetic tunneling junction element. In addition, a heat generating layer may be electrically connected in series between the first and second electrodes, and the heat generating layer may provide a relatively high resistance with respect to electrical current flow. Related methods are also discussed.

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Seoul, South Korea

Hyeong-jun Kim