Samsung Electronics Co., Ltd.

Hyeon J Jeong

Do Soo Jeong

Joon Keun Lee

Kyung Suk Kim

Heung Kyu Kwon

Kyu Jin Lee

Jin Hyuk Lee

Seung H Ahn

Ki Won Choi

Min Cheol An

Hai Jeong Sohn

Dong Y Oh

Oh-Sik Kwon

Oh Sik Kwon

Lead frames for semiconductor chips include spaced apart tie-bars which extend to contact and support the semiconductor chip. Adhesive is used between the tie-bars and the chip to adhesively couple the tie-bars to the chip. The lead frame leads therefore need not be used to adhesively couple the chip to the lead frame, thereby reducing or eliminating the need for equal spacing and close coupling of the leads, and reducing or preventing problems caused by deterioration of adhesive on the leads. The tie-bars may include polyimide tape or liquid adhesive held in cups. During fabrication, a semiconductor chip is mounted on the adhesive material, such that the tie-bars mechanically support the semiconductor chip and the lead ends extend adjacent the semiconductor chip. The lead ends are then electrically connected to the semiconductor chip and the package is encapsulated.

Lead frames including extended tie-bars, and semiconductor chip packages

A semiconductor chip package includes a semiconductor chip, a lead frame including a plurality of inner leads each having a wire bonding point on a top surface, bonding wires for electrically interconnecting the semiconductor chip to each of the plurality of inner leads, and a molding compound for encapsulating the semiconductor chip and the inner leads. Each of the plurality of inner leads of the lead frame has a means for locking movement of the molding compound against the top surfaces of the inner leads, and the locking means, for example a linear groove, down set feature of the inner lead or second wire ball, is placed in close proximity to the wire bonding.

Lead frame for a semiconductor device comprising inner leads having a

A three dimensional stack package device that can realize vertical electrical interconnection of the stacked individual package devices without a cost increase or additional complicated processing steps. The three dimensional package device includes a plurality of individual semiconductor devices, each individual semiconductor device including (1) a semiconductor chip, (2) a protective body for encapsulating the semiconductor chip, (3) a lead frame comprising inner lead portions electrically interconnected to the semiconductor chip and included within the protective body, outer lead portions formed as a single body with the inner lead portions, and coupling lead portions located between the inner and outer lead portions and having a top surface exposed upward from the protective body, and (4) a plurality of vertical interconnection elements attached to a back surface of the coupling lead portions and exposed from the protective body in a direction opposing the exposed top surface of the coupling lead portions, whereby, an electrical interconnection of the plurality of individual semiconductor devices is accomplished by the coupling lead portions and the vertical interconnection elements, and electrical interconnection of the three dimensional stack package device to an external circuit device is accomplished by the outer lead portions of a lowermost semiconductor device.

Three dimensional stack package device having exposed coupling lead

An appartus for testing bare semiconductor chips, especially for burn-in testing, includes a chip holding socket which comprises a substrate portion having at least one pair of opposing grooves formed along respective edges thereof. A pair of resilient elongate members are inserted into the grooves, and act to hold a respective bare chip in the holding socket. Preferably, a plurality of such holding sockets are mounted and electrically connected to a main test board, by which test signals are provided to test the bare semiconductor chips. A method for manufacturing such a testing apparatus is also disclosed herein.

Semiconductor chip holding device

A lead frame for a semiconductor device used in a vertically surface-mounted package which has internal leads gathered on one side thereof includes separately formed dummy leads attached to a semiconductor chip on the opposite side of the lead frame to avoid an inconsistent inflow pressure of a molding material during a package molding process caused by gathering of the internal leads on only one side, thereby enhancing reliability of the semiconductor package. There is also no need to separately form a heat sink structure for eliminating heat of the semiconductor chip since the dummy leads function as the heat sink.

Lead frame having dummy leads

A semiconductor chip package comprises leads which protrude from one side of a package body, and support portions which are formed at both ends of the package body on either side of the leads for firmly mounting the package on a printed circuit board (PCB). The support portions are made of a same material as the package body. At the package body, a slot is formed to further protect the leads, and the leads are alternately formed to mount the packages close by. Thus, there is no additional process step for forming holes in the PCB to mount the support portions of the semiconductor package, so the mounting process of the package becomes simpler. The support portions which protrude from the package body permit the package to be mounted on the PCB firmly. The slot and support portions protect the leads and prevent the leads from being deformed by external forces, thereby improving the reliability of the semiconductor package. Also, since the leads are alternately formed and the packages can be mounted near to each other, the package occupies only a small area of the PCB, thereby improving the packing density.

High density vertically mounted semiconductor package

A semiconductor lead frame is disclosed to improve the characteristics and reliability of a semiconductor device using lines of bonding pads in a cross-arrangement. The semiconductor lead frame comprises a rectangular semiconductor chip with a plurality of output terminals of associated circuits, a plurality of leads having inner and outer ends, bus bars extending around the inner ends of the leads, at least one insulator disposed between the semiconductor chip and the inner ends of the leads for electrically insulating the chip and the leads, metal wires electrically connecting the inner ends of the leads to selected and respective bonding pads and the bus bars to the pads in common. The leads are inclined relative to the lines of pads to form a line of outer terminals for the lead frame which extend over a distance exceeding the length of the chip. The semiconductor device can thereby accommodate a great number of bonding pads in response to the high density demand without increasing the size of the chip.

Growing community of inventors

Inchon, South Korea

Hyeon J Jeong