Samsung Electronics Co., Ltd.

Hyeoksang Oh

Jiyoung Kim

Jongmin Baek

Sanghoon Ahn

Kyu-Hee Han

Naein Lee

Taejin Yim

Woochoel Noh

Wonkyu Han

Gyeongyun Han

Yoonhee Kang

Embodiments of the present inventive concepts provide methods of forming an ultra-low-k dielectric layer and the ultra-low-k dielectric layer formed thereby. The method may include forming a first layer by supplying a precursor including silicon, oxygen, carbon, and hydrogen, performing a first ultraviolet process on the first layer to convert the first layer into a second layer, and performing a second ultraviolet process on the second layer under a process condition different from that of the first ultraviolet process.

Methods of forming an ultra-low-k dielectric layer and dielectric layers formed thereby

A method of fabricating a semiconductor device including an interlayer insulating layer and interconnections is provided. An interlayer insulating layer is formed on a substrate. An opening is formed in the interlayer insulating layer. A degassing process is performed by irradiating the interlayer insulating layer having the opening with microwaves. A K-value recovery process is performed by irradiating the interlayer insulating layer having the opening with UV light. A conductive layer is formed in the opening. The degassing process and the K-value recovery process are performed as an in-situ process.

Method of forming semiconductor device having dielectric layer and related system

A semiconductor integrated circuit with tilted via connection and related method are provided, the circuit including a via layer having at least one tilted via, and a wireway layer having at least one elongated wireway disposed above the via layer, wherein the wireway connects to and partially overlaps the tilted via; and the method including forming a via layer, patterning a via trench in the via layer, forming a wireway layer, patterning an elongated wireway in the wireway layer, etching the patterned wireway and the patterned via, and filling the etched wireway and the etched via with a conductive material, wherein the filled wireway partially overlaps the filled via.

Artificially tilted via connection

Growing community of inventors

Suwon-si, South Korea

Hyeoksang Oh