Samsung Electronics Co., Ltd.

Seoul National University

Hyeokjun Choe

Jeongho Lee

Younho Jeon

Younggeon Yoo

Wonseb Jeong

Jaeho Shin

Heehyun Nam

Ipoom Jeong

Sungroh Yoon

Seijoon Kim

Seongsik Park

Hyodeok Shin

Youngjin Cho

Chanho Yoon

Junghyun Hong

A storage system includes a host and a storage device. The host includes a host processor and a host memory buffer, wherein the host processor includes a CPU core controlling operation of the host and a cache dedicated for use by the CPU core. The host memory buffer includes a submission queue and a completion queue. The storage device is connected to the host through a link and communicates with the host using a transaction layer packet (TLP). The storage device includes a nonvolatile memory device (NVM) and a storage controller, wherein the host writes a nonvolatile memory express (NVMe) command indicating a destination to the submission queue, and the storage controller reads data from the NVM, directly accesses the cache in response to destination information associated with the destination, and stores the read data in the cache.

Storage system utilizing transaction layer packet contained steering information

A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.

Memory controller performing selective and parallel error correction, system including the same and operating method of memory device

A method of operating a storage device including a neural network processor includes outputting, by a controller device, a trigger signal instructing the neural network processor to perform a neural network operation in response to a command from a host device, requesting, by a neural network processor, target model data about parameters of a target model and instruction data for instructing the neural network operation to a memory device storing the target model data and the instruction data in response to the trigger signal, receiving, by the neural network processor, the target model data and the instruction data from the memory device and outputting, by the neural network processor, inference data based on the target model data and the instruction data.

Storage device and method of operating the same

In a method of allocating and protecting a memory in a computational storage device including a first computing engine and a buffer memory, a memory allocation request is received from a host device that is disposed outside the computational storage device. Based on the memory allocation request, a memory allocation operation in which a first memory region is generated in the buffer memory and a first key associated with the first memory region is generated is performed. A program execution request is received from the host device. Based on the program execution request, a program execution operation is performed in which a first program is executed by the first computing engine by accessing the first memory region based on an encryption or a decryption using the first key.

Method of allocating and protecting memory in computational storage device, computational storage device performing the same and method of operating storage system using the same

A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

System, device and method for accessing device-attached memory

An interface circuit includes: a packet transmitter configured to generate a plurality of transmission packets based on a request, which is output from a core circuit, and output the plurality of transmission packets, the plurality of transmission packets including information indicative of being a packet to be merged; and a packet receiver configured to generate a merged packet by merging a plurality of extension packets from among a plurality of reception packets received from outside the interface circuit, the plurality of extension packets including information indicative of being a packet to be merged.

Interface circuit for providing extension packet and processor including the same

A memory device is configured to communicate with a plurality of host devices, through an interconnect, and includes a memory including a plurality of memory regions that includes a first memory region that is assigned to a first host device and a second memory region that is assigned to a second host device. The memory device further includes a direct memory access (DMA) engine configured to, based on a request from the first host device, the request including a copy command to copy data that is stored in the first memory region to the second memory region, read the stored data from the first memory region, and write the read data to the second memory region without outputting the read data to the interconnect.

Memory device including direct memory access engine, system including the memory device, and method of operating the memory device

A storage device includes a plurality of non-volatile memories; a volatile memory; a computing device configured to perform an operation on data provided by the plurality of non-volatile memories; and a storage controller including a resource manager configured to receive information about priority of tenants from a host, and to dynamically set resources of the plurality of non-volatile memories, the volatile memory, and the computing device based on the priority.

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Hwaseong-si, South Korea

Hyeokjun Choe