Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Hyeokjong Lee

Kyungmin Kim

Yunhwan Jung

Sunyool Kang

Yunhong Kim

Yongsuk Choi

Ingyeong Shin

Kihyuk Kim

Jaeseok Kim

Se-jun Kim

Soowon Park

Incheol Kang

JinHo Seo

Byung-jo Kim

Inho Hwang

Changheon Lee

Hyuntae Lee

Seogheon Ham

Jahyun Koo

Disclosed is a counter which generates a binary code and a digital signal The counter includes: a reset memory circuit configured to store a sum of N reset binary codes, each of the N reset binary codes corresponding to a result of comparing a reset signal of the pixel signal with the ramp signal, and to calculate one of the N reset binary codes by performing a shifting operation on the sum of the N reset binary codes; and an output memory circuit configured to output the digital signal based on the N reset binary codes, a first image binary code indicating a result of comparing a first image signal of the pixel signal with the ramp signal once, and N sum binary codes, the N sum binary codes respectively indicating N results of comparing a sum signal of the pixel signal with the ramp signal.

Image sensor including counter performing shifting operation and operation method thereof

Provided is a semiconductor device. The semiconductor device includes a first counter latch circuit configured to receive a count code and to latch the count code according to a comparison result signal; and a second counter latch circuit configured to receive the count code from the first counter latch circuit, and to latch the count code by using a plurality of first latches. The first latches are coupled in series to each other and are configured to operate to sequentially bypass values transmitted to the respective first latches.

Semiconductor device

An image sensor includes a pixel configured to operate in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode during a readout period, and a correlated double sampling (CDS) circuit configured to generate a comparison signal based on a ramp signal and a pixel voltage received from the pixel, wherein the CDS circuit includes a comparator configured to: receive the pixel voltage through a first input node, receive the ramp signal through a second input node based on an LCG reset signal or an LCG image signal being received as the pixel voltage, and receive the ramp signal through a third input node based on an HCG reset signal or an HCG image signal being received as the pixel voltage; and compare the ramp signal to the pixel voltage, and output the comparison signal corresponding to a comparison result.

Image sensor with high conversion gain (HCG) mode and low conversion gain (LCG) mode

A gray code-to-binary code converter includes multiple parallel-in parallel-out (PIPO) latches, each of the multiple PIPO latches configured to output a parallel output gray code by latching a parallel input gray code in response to a sampling signal, and a parallel-in serial-out (PISO) circuit including a first group of switches, the PISO circuit configured to convert the parallel output gray code, which is latched in the multiple PIPO latches, into a binary code, and sequentially output bits of the binary code in units of bit, from a least significant bit (LSB) of the binary code to a most significant bit (MSB) of the binary code, while changing an arrangement of the first group of switches.

Gray code-to-binary code converter and devices including the same

A correlated double sampling (CDS) circuit, an operating method thereof, and an image sensor including the CDS circuit are disclosed. The CDS circuit includes a first comparator configured to operate based on a first bias current, and compare, with a ramp signal, a pixel voltage that is output from a pixel, during a first period and a fourth period during which the pixel operates in a low conversion gain (LCG) mode, a second comparator configured to operate based on a second bias current, and compare, with the ramp signal, the pixel voltage output from the pixel, during a second period and a third period during which the pixel operates in a high conversion gain (HCG) mode, the second period being after the first period, the third period being after the second period, and the fourth period being after the third period.

CDS circuit, operating method thereof, and image sensor including CDS circuit

An image sensor including: a plurality of phase shift code generators, wherein each of the plurality of phase shift code generators outputs a phase shift code; a. test data selection circuit for outputting test data corresponding to a test pattern; a counter for receiving the phase shift code from at least one of the plurality of phase shift code generators, receiving the test data from the test data selection circuit, latching a digital code corresponding to the test pattern using the phase shift code, and outputting the digital code; and a control logic for calculating a data pattern using the digital code and selecting one of the plurality of phase shift code generators in accordance with a result of a comparison between the data pattern and the test pattern.

Image sensor

An image sensor includes a pixel sensor outputting an analog sampling signal; a sampling unit comparing the sampling signal and a ramp signal, and outputting a comparison signal that is time-axis length information; and a counter counting a length of the comparison signal based on a clock signal and first and second complement control signals. The counter includes an AND gate ANDing the comparison signal and the clock signal; and a counting unit triggered at a falling edge of the AND gate output to output a count value. The counting unit includes a complement operation controller storing an inverted count value that is an inversion of the count value in response to the first complement control signal, and outputting the inverted count value in response to the second complement control signal; and a D-flip-flop that is set or reset depending on the inverted count value, and outputs the count value.

Counter circuit and image sensor including the same

CDS circuit, operating method thereof, and image sensor including CDS  circuit

An image sensor including: a plurality of phase shift code generators, wherein each of the plurality of phase shift code generators outputs a phase shift code; a test data selection circuit for outputting test data corresponding to a test pattern; a counter for receiving the phase shift code from at least one of the plurality of phase shift code generators, receiving the test data from the test data selection circuit, latching a digital code corresponding to the test pattern using the phase shift code, and outputting the digital code; and a control logic for calculating a data pattern using the digital code and selecting one of the plurality of phase shift code generators in accordance with a result of a comparison between the data pattern and the test pattern.

An analog-to-digital converter for converting a pixel signal generated from sensed light into a digital signal includes a comparator configured to compare the pixel signal with a ramp signal having a constant slope to generate a comparison signal; a delay circuit configured to generate a first signal corresponding to the comparison signal, the delay circuit including a plurality of delay elements configured to generate a second signal by delaying the first signal by a first time period; and a compensator circuit configured to measure a period of the comparison signal to output a delay select signal to the delay circuit based on the measured period, the delay select signal delaying the first signal by the first time period, wherein the first time period is obtained by dividing the period of the comparison signal.

Analog-to-digital converter including delay circuit and compensator, image sensor including the analog-to-digital converter, and method of operating the same

A laundry treating apparatus comprises a cabinet forming a profile, provided with a laundry opening; a door having an inner frame arranged toward the laundry opening and an outer frame coupled to the inner frame and arranged toward the outside of the cabinet, and opening and closing the laundry opening; a hinge part having a first pivot rotating the door along a first rotational direction and a second pivot rotating the door along a second rotational direction different from the first rotational direction; a pivot switching member movable to rotatably fix the door to any one of the first pivot and the second pivot; and a pressing piece provided in the door and pressed by a user to move the pivot switching member, wherein the pressing piece includes a pressing point pressed by the user, and the pressing point is provided at an upper end of the pressing piece.

Laundry treating apparatus

An image sensor in accordance with exemplary embodiments of the inventive concept may include a pixel sensor array which includes an active pixel sensor and an optical black pixel sensor; a first analog to digital converter configured to convert a first sensing signal, which is provided from the active pixel sensor, to a first digital signal; a second analog to digital converter configured to convert a second sensing signal, which is provided from the optical black pixel sensor, to a second digital signal; and an output buffer configured to temporarily store and output the first digital signal and the second digital signal, wherein a plurality of noise characteristics of the second analog to digital converter is different from a plurality of noise characteristics of the first analog to digital converter.

Image sensor including heterogeneous analog to digital convertor with different noise characteristics

Provided is an image sensor including a sensor array including a plurality of pixels arranged in rows and columns. The image sensor may include a ramp signal generator which may generate a ramp signal. The intensity of the ramp signal may increase or decrease in response to a ramp enable signal. The image sensor may include an analog-digital converter electrically connected to one of the columns of the pixels. The analog-digital converter may be configured to compare an output signal from the one of the columns of the pixels with the ramp signal, thereby generating time information. The analog-digital converter may be configured to convert the time information to digital information in response to a counter enable signal. An activation of the counter enable signal may be delayed by a predetermined time delay, compared with that of the ramp enable signal.

Growing community of inventors

Suwon-si, South Korea

Hyeokjong Lee