Samsung Electronics Co., Ltd.

International Business Machines Corporation

Infineon Technologies Ag

Advanced Micro Devices Corporation

Hyeok-Sang Oh

Young-Bae Kim

Sang-Hoon Ahn

Sung-Jin Kang

Hoon-Seok Seo

Woo-Jin Lee

Su-Hyun Bark

Tien-Jen Cheng

Jung-Woo Lee

Bum-Ki Moon

Woo-Jin Jang

Minseok Oh

Eui-Bok Lee

Dae-Keun Park

Ji-Hong Choi

Ki-Ho Kang

Kyoung-woo Lee

Jong-Min Baek

Deok-Young Jung

Il-Goo Kim

Jeong-Hoon Ahn

Woo-Kyung You

Vietha Nguyen

Ju-hyuck Chung

Sang-Shin Jang

Jun-Jung Kim

Jin-Hyeung Park

Hyo-Seon Lee

Suk-Hee Jang

An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

Integrated circuit device and method of manufacturing the same

Provided herein is a method of forming micropatterns, including: forming an etching target film on a substrate; forming a photosensitivity assisting layer on the etching target film, the photosensitivity assisting layer being terminated with a hydrophilic group; forming an adhesive layer on the photosensitivity assisting layer, the adhesive layer forming a covalent bond with the hydrophilic group; forming a hydrophobic photoresist film on the adhesive layer; and patterning the photoresist film.

Methods of forming micropatterns and substrate processing apparatus

An integrated circuit (IC) device includes a lower wiring structure including a lower metal film. The lower wiring structure penetrates at least a portion of a first insulating film disposed over a substrate. The IC device further includes a capping layer covering a top surface of the lower metal film, a second insulating film covering the capping layer, an upper wiring structure penetrating the second insulating film and the capping layer, and electrically connected to the lower metal film, and an air gap disposed between the lower metal film and the second insulating film. The air gap has a width defined by a distance between the capping layer and the upper wiring structure.

A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.

Wiring structures and semiconductor devices

Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby

Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step is formed in the etch-stop layer by removing portions of the exposed etch-stop layer. And, the step is formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer. Portions of the interlayer dielectric layer are removed to expose portions of the raised portion of the etch-stop layer. And, the exposed recessed and raised portions are anisotropically etched to expose the lower conductive layer and to form the interconnection hole having the slopes, wherein the slopes are made of a residual etch-stop layer at the lower sides of the interconnection hole.

Methods of fabricating semiconductor device having slope at lower sides of interconnection hole with etch-stop layer

In a method of fabricating a dual damascene interconnection, a reliable trench profile is secured. The method includes forming a lower interconnect feature on a substrate, forming a dielectric layer on the lower interconnect feature, forming a hard mask on the dielectric layer, forming a via in the dielectric layer using the hard mask as an etch mask, forming a trench hard mask defining a trench by patterning the hard mask, forming a trench, which is connected with the via and in which an upper interconnection line is formed, by partially etching the dielectric layer using the trench hard mask as an etch mask, removing the trench hard mask using wet etch, and forming an upper interconnection line by filling the trench and the via with an interconnection material.

Method of fabricating dual damascene interconnection

Growing community of inventors

Suwon-si, South Korea

Hyeok-Sang Oh