Samsung Electronics Co., Ltd.

Hyeok-Man Kwon

Young-Jun Kwon

Jun-whan Ahn

Ki-Young Choi

Sun-gyeum Kim

Tae-Je Cho

Yun-seok Choi

Nak-hee Seong

Cha-jea Jo

Seung-Hong Jeon

Provided is a system including a multi channel memory and an operating method for the same. The multi channel memory may include a respective set of memories, wherein each set may include one or more memories. The operating method includes receiving access requests including system addresses for a multi channel memory having 2channels, where n is a natural number greater than 0, allocating a first channel of the 2channels based on n+1 or more bits of a first address of the system addresses, and performing an access of a respective set of memory devices through the allocated first channel.

System including multi channel memory and operating method for the same

In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Semiconductor memory device including non-volatile memory, cache memory, and computer system

Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip.

Stacked semiconductor package

Growing community of inventors

Suwon-si, South Korea

Hyeok-Man Kwon