Samsung Electronics Co., Ltd.

Hyeok-jong Lee

Se-jun Kim

Won-Ho Choi

Jin-Woo Kim

Hee-Sung Chae

Chang-Eun Kang

Yun-hong Kim

Jae-jung Park

Provided are an image sensor and an image processing device including the same. The image sensor includes: a pixel array including a plurality of pixels arranged in rows and columns and configured to generate pixel signals from the plurality of pixels, a time calculator configured to receive zoom information corresponding to digital zooming, and configured to calculate a row processing time available for processing the pixel signals from the plurality of pixels included in a single row based on the zoom information, a timing generator configured to generate at least one control signal based on the row processing time; and an Analog-to-Digital Converter (ADC) configured to generate pixel data by performing sampling on the pixel signals according to the at least one control signal.

Image sensor having a time calculator and image processing device including the same

In a method of operating an image sensor, the image sensor includes a pixel array and a plurality of column driving circuits that are connected to a plurality of columns of the pixel array. A test operation is performed by applying a test pattern to the plurality of column driving circuits while changing a level of a well-bias voltage applied to a transistor included in the plurality of column driving circuits. A bias setting operation for setting the level of the well-bias voltage is performed based on a result of the test operation. An image capture operation for detecting incident light and generating a frame image is performed based on the pixel array, the plurality of column driving circuits and the well-bias voltage set by the bias setting operation.

Method of operating an image sensor, image sensor performing the same, and electronic system including the same

A digital correlated double sampling (CDS) circuit includes a first latch circuit, a first converting circuit, a second converting circuit, a second latch circuit, and a calculating circuit. The first latch circuit latches an input phase shift code based on a first control signal to store first and second phase shift codes. The first converting circuit converts the first and second phase shift codes into first and second Gray codes. The second converting circuit converts the first Gray code and the second Gray code into a first binary code and a second binary code. The second latch circuit latches an output of the second converting circuit based on a second control signal to store the first binary code. The calculating circuit operates on the first binary code and the second binary code to generate a third binary code, and outputs the third binary code.

Digital correlated double sampling circuits and image sensors including the same

An image sensor includes a pixel array including a plurality of pixels, an analog-to-digital converter having a first counter for converting an analog signal into a digital signal, and an output buffer having a first memory. A first counter test result value generated as a test result for the first counter is stored in the first memory in a test mode. The output buffer outputs the first counter test result value from the first memory to an outside of the output buffer in response to a first selection signal. The output buffer further includes a reset logic circuit for resetting the first memory depending on whether the first counter test result value is output or not. The plurality of pixels generate the analog signal in response to incident light.

Image sensor with test circuit

An integrated circuit counter includes a cascaded chain of bit counters, which are collectively configured to count a number of first edges of a counter input signal received at an input thereof and output the count as a counter output signal. The cascaded chain includes at least two bit counters, which are: (i) configured to support both counter and buffer modes of operation, and (ii) responsive to respective bypass control bit signals having values that specify whether a corresponding one of the at least two bit counters is disposed in the counter or buffer mode of operation.

Counter circuit and image sensor including the same

A digital correlated double sampling (CDS) circuit includes a first latch unit, a second latch unit and a calculating unit. The first latch unit stores digital reset component data and digital image component data by latching a count signal in response to a first control signal. The second latch unit stores the digital reset component data by latching an output of the first latch unit in response to a second control signal. The calculating unit generates digital effective image data by subtracting the digital reset component data from the digital image component data.

Digital correlated double sampling circuit and image sensor including the same

A ramp signal generator includes a rising-edge current unit, a falling-edge current unit and a current-voltage converter. The rising-edge current unit provides a rising-edge output current that sequentially increases or decreases in synchronization with rising edges of a clock signal. The falling-edge current unit provides a falling-edge output current that sequentially increases or decreases in synchronization with falling edges of the clock signal. The current-voltage converter outputs a ramp voltage by converting a summed current of the rising-edge output current and the falling-edge output current.

Ramp signal generator and image sensor including the same

A line driving circuit in which a signal characteristic is improved and a semiconductor device including the same are provided. The semiconductor device includes: a line controller arranged in a first portion of at least one line; a first driver arranged in the first portion and configured to output through the at least one line a first signal according to a control of the line controller; and a second driver arranged in a second portion of the at least one line and configured to output through the at least one line a second signal according to a level of the first signal.

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Yongin-si, South Korea

Hyeok-jong Lee