Skhynix Inc.

Hyeng Ouk Lee

Sang Kwon Lee

Keun Soo Song

Yong Deok Cho

Seung Chan Kim

A smart vehicle system is disclosed, which relates to technology for increasing efficiency of a vehicle-embedded memory. The smart vehicle system includes a host and a storage device. The host selects any one of a first mode and a second mode according to operation, process or workload of a vehicle, and transmits and receives data through different channels in response to the first mode and the second mode. The storage device stores the data received through different channels in the first core circuit and the second core circuit, or reads the data stored in the first core circuit and the second core circuit. The storage device executes different operations in the first mode and the second mode in a manner that an operation to be executed in the first mode is different from an operation to be executed in the second mode.

Smart vehicle system with data processing apparatus

A semiconductor device and a semiconductor system including the same are disclosed. The semiconductor system includes a first semiconductor device having a memory region, the first semiconductor device configured to output reliability information of the memory region to an external part, and a second semiconductor device configured to control the first semiconductor device based on the reliability information.

Semiconductor device and semiconductor system including the same

A semiconductor apparatus includes a detection voltage generation circuit configured to generate a first detection voltage and a second detection voltage of which voltage levels are varied according to characteristics of a PMOS transistor and an NMOS transistor in response to a detection enable signal, a code generation circuit configured to generate a detection code in response to the voltage levels of the first and second detection voltages, a reference voltage generation circuit configured to generate a reference voltage in response to the detection code, an internal voltage generation circuit configured to generate an internal voltage in response to the reference voltage, and an internal circuit configured to operate by receiving the internal voltage.

Semiconductor apparatus

A refresh time detection circuit and a semiconductor device including the same may be provided. The refresh time detection circuit may include a code generator configured to generate a code signal for detecting a refresh time. The refresh time detection circuit may include a latch circuit configured to generate a latch signal by latching the code signal according to a fail signal, and generate a pre-code signal and a post-code signal by latching each latch signal according to a pre-enable signal and a post-enable signal. The refresh time detection circuit may include a subtractor configured to output a refresh detection signal by performing subtraction between the pre-code signal and the post-code signal. The refresh time detection circuit may include a comparator configured to generate a detection signal by comparing the refresh detection signal with an offset signal based on the post-enable signal.

Refresh time detection circuit and semiconductor device including the same

A semiconductor device includes a temperature code latch circuit and a period selection circuit. The temperature code latch circuit latches a count code having a logic level combination corresponding to an internal temperature to output the latched count code as a temperature code. The period selection circuit selects a period of a refresh signal in response to the temperature code. A period variation rate of the refresh signal according to variation of the internal temperature is controlled by a first gradient selection signal in a first temperature section and is controlled by a second gradient selection signal in a second temperature section.

Semiconductor device generating a refresh signal

A power control is disclosed, which relates to a technology for stably performing a power ramp-up operation during a power-up operation of an integrated circuit (IC) having heterogeneous power. The power control device includes: an amplifier configured to perform level shifting of a second power-supply voltage level to a first power-supply voltage level according to an input signal during an initial power-up operation section, and output the level-shifted output signal; an initialization unit configured to set an output signal level of the amplifier to the first power-supply voltage level according to a control signal during the initial power-up operation section, and output the first power-supply voltage level; and a latch unit configured to latch an output signal of the initialization unit according to the second power-supply voltage level during the initial power-up operation section.

Power control device

A self-refresh device is disclosed, which relates to a technology for generating a self-refresh period by reflecting refresh characteristics of an actual cell in a semiconductor device. The self-refresh device includes: a period generation unit configured to output a period control signal by comparing an output voltage of a dummy cell with a reference signal; a phase detection unit configured to detect a phase of the period control signal in response to an oscillation signal having a fixed period; and a refresh signal output unit configured to output a self-refresh period signal in response to the oscillation signal and an output signal of the phase detection unit.

Self-refresh device and semiconductor device including the self-refresh device

A semiconductor system including a semiconductor circuit configured to compare a first error detection code generated by performing an operation on read data to a second error detection code and determine a data transmission error, and a controller configured to provide the second error detection code, generated by performing an operation on expect data based on the read data, to the semiconductor circuit.

Semiconductor system with error detection

The semiconductor device includes a first data aligner, an input strobe signal generator and a second data aligner. The first data aligner aligns input data in synchronization with an internal strobe signal to generate alignment data. The input strobe signal generator generates first and second delay signals from the internal strobe signal. The input strobe signal generator also latches an input clock signal generated from an external clock signal after a write latency period from a period when a write operation commences, in response to the first and second delay signals to generate an input strobe signal. The second data aligner re-aligns the alignment data in synchronization with the input strobe signal to generate internal data.

Semiconductor devices including data aligner

Serializers are provided. The serializer includes a first drive control signal generator and a second drive control signal generator. The first drive control signal generator amplifies a first input data signal in response to a first clock signal and a second clock signal to generate a first pull-up drive control signal and a first pull-down drive control signal. The second drive control signal generator amplifies a second input data signal in response to the second clock signal and a third clock signal to generate a second pull-up drive control signal and a second pull-down drive control signal.

Serializers

A semiconductor memory apparatus includes a data input enable signal generation block configured to sequentially delay a data strobe signal to generate a first delayed data strobe signal, a second delayed data strobe signal, a third delayed data strobe signal and a fourth delayed data strobe signal, and generate a data strobe enable signal in response to a CAS write signal, a CAS write latency signal and the first to fourth delayed data strobe signals, a latch control signal generation block configured to output the data strobe signal as a latch control signal during an enable period of the data strobe enable signal, and a data latch block configured to latch data in response to the latch control signal and output latched data.

Growing community of inventors

Yongin-si, South Korea

Hyeng Ouk Lee