Lg Display Co., Ltd.

Hyelim Ji

Yongseok Park

YongSeok Park

Yewon Hong

Yeonkyung Kim

SungSoo Shin

Sohee Choi

A display panel and a display device having an emission control driver are discussed. The display device can include a display panel to display an image through sub pixels, a scan driver to supply a second scan signal to each of second gate lines, and an emission control driver to supply an emission control signal to each of third gate lines and supply a first scan signal to each of first gate lines. Each emission control stage of the emission control driver can include an output buffer. The output buffer can output an emission control signal to an output line and output a first scan signal to a scan output line under control of a first control node, and output a high potential power supply voltage to the output line and output a low potential power supply voltage to the scan output line under control of a second control node.

Display panel and display device having emission control driver

A display device can include a display panel configured to display an image through sub pixels, a first scan driver configured to supply a plurality of first scan signals to a plurality of first gate lines connected to the sub pixels, and an emission control driver configured to supply a plurality of emission control signals to a plurality of third gate lines connected to the sub pixels. The emission control driver includes a plurality of emission control stages configured to supply the plurality of emission control signals, respectively. Each of the plurality of emission control stages can include an output buffer including a first output transistor configured to output a clock signal to an output line by controlling a Q node, and a second output transistor configured to output a high potential power supply voltage to the output line by controlling a QB node.

Display device having emission control driver

Provided are a shift register and display apparatus including the same. A shift register includes a plurality of stages, each of the plurality of stages including: a node controller configured to: periodically discharge a first node voltage generated from a first driving voltage during a first voltage level of a clock signal, and control a second node voltage opposite to the first node voltage based on a second driving voltage, and an output part configured to receive the clock signal to output an output signal based on the first node voltage.

Shift register and display apparatus including the same

A gate driver and a display device using the same are disclosed. The gate driver includes a plurality of stages connected in a cascade connection manner, and each of the stages include a clock input configured to receive a shift clock signal, a first output terminal, and a second output terminal. Each of the stages generates a first output voltage that is transmitted to another stage through the first output terminal and a second output voltage that is supplied to a gate line of a display panel through the second output terminal. Each of the stages includes a first diode connected between the clock input and the first output terminal.

Gate driver and display device using the same

A display apparatus can include a first transistor disposed on a substrate, the first transistor including a first active layer made of low temperature polycrystalline silicon (LTPS); a circuit insulating layer disposed on the first transistor; a second transistor disposed on the circuit insulating layer, the second transistor including a second active layer made of an oxide semiconductor; a driving transistor disposed on the circuit insulating layer, the driving transistor having a back channel etch structure (BCE) and an active layer made of the oxide semiconductor; and a light emitting diode electrically connected to the driving transistor, in which the circuit insulating layer is disposed between the first transistor and the driving and second transistors.

Display apparatus

A display apparatus includes a plurality of pixels each including an organic light emitting device and a pixel driving circuit. The pixel driving circuit includes a driving transistor controlling a driving current flowing in the organic light emitting device and a first, second, third, fourth, and fifth switching transistor, the third switching transistor selectively connecting a second node which is a drain electrode of the driving transistor to a third node which is a gate electrode of the driving transistor. The third switching transistor differs from a type of each of the driving transistor and the first, second, fourth, and fifth switching transistors. Accordingly, even when the organic light emitting display apparatus is driven at a low frequency, a bezel area is reduced, and a high resolution of a display panel is realized.

Organic light emitting display apparatus

Disclosed herein is a liquid crystal display device capable of improving reliability of a gate in panel (GIP) type gate driving circuit by improving positive bias temperature stress (PBTS) characteristics of a thin film transistor in the gate driving circuit. The liquid crystal display device may include a first substrate including a thin film transistor of a GIP circuit, and an opaque electrode line that overlaps a semiconductor active layer of the thin film transistor. A backlight unit is included, and a second substrate is positioned between the backlight unit and the first substrate. The second substrate includes a black matrix having an opening that transmits light emitted from the backlight unit. In operation, the opaque electrode line blocks a portion of the light transmitted through the opening of the black matrix, and another portion of the light transmitted through the opening of the black matrix is transmitted to the semiconductor active layer.

Liquid crystal display device

A gate driver and a display device using the same are disclosed. The gate driver includes a first transistor configured to pre-charge a Q node, a second transistor configured to raise the output voltage depending on a voltage of the Q node, a third transistor configured to charge a QB node, a fourth transistor configured to lower the output voltage depending on a voltage of the QB node, and a capacitor connected between a gate and a source in at least one of the second transistor and the third transistor. The capacitor has a capacitance greater than a capacitance between the gate and a drain of the transistor to which the capacitor is connected. The capacitor includes an upper capacitor disposed on an organic passivation layer covering the transistors.

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Paju-si, South Korea

Hyelim Ji