Hynix Semiconductor Inc.

Skhynix Inc.

Hye-Young Lee

Kie-Bong Ku

Yong-Mi Kim

Sung-Hwa Ok

Se-Jin Yoo

Choung-Ki Song

A semiconductor device includes a data bus inversion (DBI) decision unit suitable for deciding whether a DBI operation mode is performed, based on a read data, and generating a DBI decision signal corresponding to a result of the decision; an output control unit suitable for generating an arrangement control signal in which a delay amount of time for the decision is reflected, in a DBI operation mode; a data synchronization unit suitable for synchronizing the read data with the arrangement control signal and output the synchronized read data and inverted signals of the synchronized read data, in the DBI operation mode; and a data output unit suitable for selectively outputting the synchronized read data and the inverted signals of the synchronized read data, to an external in response to the DBI decision signal, the arrangement control signal and an output control signal, in the DBI operation mode.

Semiconductor device

A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode, and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode.

A delay locked loop includes a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal and a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal.

Delay locked loop

A filtering circuit includes jitter determination reference control unit configured to determine a jitter determination reference in correspondence to an operation mode and output a control signal in response to the jitter determination reference, and a filtering unit configured to set the jitter determination reference in response to the control signal and determine whether an input signal is maintained during a sample period in response to the set jitter determination reference.

Filtering circuit and semiconductor integrated circuit having the same

A delay locked loop circuit includes a delay replica model unit for reflecting a delay time of an actual output path to a source clock and outputting the reflected source clock as a delay replica clock, a detector for detecting a remaining time after subtracting a time corresponding to a multiple of a clock cycle of the source clock from a time corresponding to a phase difference between the delay replica clock and the source clock, and a delay locking unit for delaying the source clock for a delay time to synchronize a clock generated by delaying the source clock for the detected remaining time of the detector with a phase of the source clock.

Delay locked loop circuit and operation method thereof

A delay locked loop (DLL) of a semiconductor device includes: a first delay line for delaying a first clock signal in synchronization with a first edge of an external clock signal to output a first delayed clock signal; a second delay line for delaying a second clock signal in synchronization with a second edge of the external clock to output a second delayed clock signal; a duty cycle corrector (DCC) for mixing phases of the first and second delayed clock signals to output a DLL clock signal with a corrected duty cycle; and a DCC controller for disabling the duty cycle corrector in a section during which a phase difference between the first and second delayed clock signals is greater than a preset time after a delay locking.

Growing community of inventors

Gyeonggi-do, South Korea

Hye-Young Lee