Electronics and Telecommunications Research Institute

Korea University Industrial Academic Collaboration Foundation

Hye Yeon Ryu

Jong Dae Kim

Jae Woo Lee

Kang Ho Park

Eun Kyoung Kim

Hong Yeol Lee

Seung Eon Moon

Jong Hyurk Park

Gyu Tae Kim

Jung Hwan Huh

Provided is a method of fabricating a nano-wire array, including the steps of: depositing a nano-wire solution, which contains nano-wires, on a substrate; forming a first etch region in a stripe shape on the substrate and then patterning the nano-wires; forming drain and source electrode lines parallel to each other with the patterned nano-wires interposed therebetween; forming a plurality of drain electrodes which have one end connected to the drain electrode line and contact at least one of the nano-wires, and forming a plurality of source electrodes, which have one end connected to the source electrode line and contact the nano-wires that contact the drain electrodes; forming a second etch region between pairs of the drain and source electrodes so as to prevent electrical contacts between the pairs of the drain and source electrodes; forming an insulating layer on the substrate; and forming a gate electrode between the drain and source electrodes contacting the nano-wires on the insulating layer. Accordingly, even in an unparallel structure of nano-wires to electrode lines, a large scale nano-wire array is practicable and applicable to an integrated circuit or display unit with nano-wire alignment difficulty, as well as to device applications using flexible substrates.

Method of fabricating nano-wire array

Growing community of inventors

Seoul, South Korea

Hye Yeon Ryu