Skhynix Inc.

Hye Mi Kang

Eu Joon Byun

Joo Young Lee

Dong Hoon Lee

Hyun Tae Kim

Byung Jun Kim

Hoe Seung Jung

Chi Heon Kim

Sae Gyeol Choi

A memory system comprises a memory device configured to store data; and a memory controller configured to: classify and store access data for plural pieces of map information respectively, according to a cycle; assign different weights to plural pieces of access data, classified according to the cycle, to determine a priority of the plural pieces of map information; and transmit at least one map information to a host based on the priority.

Memory controller performing map information management

A data storage device may include a storage and a controller. The storage a storage including a first region of a first physical address range and a second region of a second physical address range. The controller may generate map data including a plurality of map segments, a first segment entry and a second segment entry, and store, in the second region, the map data except for a first map segment. Each of the map segments includes a set of physical addresses corresponding to a plurality of sequential logical addresses. The first segment entry includes a first segment physical address associated with the first map segment and belonging to the first physical address range, and the second segment entry includes a second segment physical address associated with a second map segment and belonging to the second physical address range.

Data storage device and method of operating the same

A memory system includes a memory device and a controller. The memory device includes a plurality of memory blocks. The controller recognizes a change in a pattern of a plurality of write data, delays a checkpoint operation associated with a write operation regarding the plurality of write data entries when operational data regarding the plurality of write data entries is within a range that is capable of being stored in a buffer, and performs the checkpoint operation when the operational data is beyond the range.

Memory device and operation method for generating check points based on write data pattern

A storage device may determine a target data segment from among a plurality of data segments, execute a hash function on the target data segment, and cache the target data segment in a data segment cache based on a result of executing the hash function on the target data segment. The data segment cache may be a hash table including N buckets each of which is able to cache one or more data segments. The hash function may be a function which outputs an index of the target bucket based on N, an index of the target data segment, and a seed value.

Storage device for caching data segment in hash-based data segment cache and operating method of the storage device

A storage device may dynamically allocate, to a buffer, at least one among M number of buffer units each capable of storing at least one of a plurality of L2P mapping units. When receiving, from an external device, a mapping unit command requesting one or more target L2P mapping units among the plurality of L2P mapping units, the storage device may store the target L2P mapping units in the buffer before transmitting the target L2P mapping units to the external device.

Storage device for managing buffer storing a logical to physical mapping unit, and method for operating the same

A memory controller includes: a program operation controller configured to control a memory device to store data and individual mapping information; a mapping information storage configured to store therein mapping information; a mapping information update controller configured to control the memory device to store the mapping information in a second memory block; perform an update operation of updating the mapping information, and delay, when sequentiality of a predetermined number or more of logical addresses is maintained with respect to the predetermined time, the update operation until the sequentiality is broken; and a Sudden Power Off Recovery (SPOR) controller configured to receive the individual mapping information, recover the mapping information for the data stored in the page during a delay section and provide the recovered mapping information to the mapping information storage.

Storage device including memory controller and operating method thereof

An electronic device includes a memory system having improved performance. The memory system includes a memory device including memory blocks allocated to zones, a memory controller configured to send, to a host, a request for information on whether to perform a garbage collection operation on a target zone according to a trigger signal for performing a first internal operation, the target zone corresponding to a target memory block on which the first internal operation is to be performed, the target zone being included in the zones, and the host configured to provide the information on whether to perform the garbage collection operation to the memory controller based on information related to the zones, in response to the request. The memory controller determines whether to perform the first internal operation on the target memory block, based on the information on whether to perform the garbage collection operation.

Memory system performing garbage collection operation by exchanging information related to garbage collection with host and method of operating the memory system

A memory controller includes a data detection circuit configured to detect, when power is supplied after a sudden power-off (SPO), a lost write sequence index 'M' among the plural write sequence indexes, and detect first data corresponding to a write sequence index “M−1” and second data corresponding to a write sequence index “M+1”; a barrier decision circuit configured to determine, based on whether first barrier information of the first data and second barrier information of the second data are identical with each other, whether a barrier request for the first data has been received from a host; and a data recovery operation determination circuit configured to determine whether to perform a recovery operation on target data corresponding to the write sequence index “M+1” and thereafter based on whether the barrier request for the first data has been received.

Memory controller and operating method thereof

The present technology relates to a storage device. According to the present technology, a memory controller controlling a memory device including a plurality of memory blocks may include an operation controller and a lifetime information controller. The operation controller may control the memory device to receive a write request from a host and perform a write operation on a selected memory block among the plurality of memory blocks. The lifetime information controller may generate lifetime information including a lifetime level of the selected memory block based on an erase and write count of the selected memory block.

Storage device and method of operating the same

Disclosed are a data processing system comprising: a memory system for providing a host with a memory map segment including map pieces; and the host for storing the memory map segment as a host map segment and converting a logical address into a physical address using the host map segment. The memory system stores changed map pieces in a map cache, inserts the changed map pieces in a response to a first command, and provides the host with the response. The host updates the host map segment based on the changed map pieces. When a read command includes a logical address and a physical address, the memory system accesses a memory device using the physical address of the read command according to whether the logical address of the read command is stored in the map cache.

Memory system, data processing system including the same, and operating method thereof

A memory controller for controlling a memory device which stores logical-to-physical (L2P) segments includes a map data storage and a map manager. The map data storage stores a plurality of physical-to-logical (P2L) segments including mapping information between a physical address of the memory device in which write data is to be stored and a logical address received from a host, in response to a write request received from the host. The map manager updates the L2P segments stored in the memory device, based on target P2L segments corresponding to a write command provided to the memory device, which have a higher priority than the other P2L segments among the plurality of P2L segments. Each of L2P segments includes mapping information between a logical address and a physical address of data stored in the memory device.

Memory controller managing map data and operating method thereof

A data storage apparatus includes storage including a plurality of memory blocks and a controller configured to set an attribute of each of the memory blocks as a random memory block or a sequential memory block, and to manage validity of map data for data stored in each of the memory blocks using a map segment bitmap. The controller configures at least one memory block set by combining a set number of memory blocks, as a housekeeping event is triggered, and selects a victim block set from the at least one memory block set based on continuity of a logical address, or a number of valid map data, or both.

Data storage apparatus and operating method thereof

The present technology relates to an electronic device. A memory controller according to the present technology may include a host interface controller, a plurality of buffers, and a memory operation controller. The host interface controller may sequentially generate a plurality of commands based on a request received from a host. The plurality of buffers may store the plurality of commands according to command attributes. The memory operation controller may compare a sequence number of a target command stored in a target buffer among the plurality of buffers with a sequence number of a standby command stored in remaining buffers, and may determine a process of the target command and a process of the standby command based on a comparison. wherein a buffer satisfying a flush condition among the plurality of buffers is selected as the target buffer.

Growing community of inventors

Gyeonggi-do, South Korea

Hye Mi Kang