Hynix Semiconductor Inc.

Hye Jin Seo

Keum Bum Lee

Yong Seok Eun

Su Ho Kim

An Bae Lee

Kyoung Bong Rouh

Eun Ah Lee

Su Jin Chae

Hyung Suk Lee

Yong Soo Joung

Dong-Su Park

Cheol-Hwan Park

The manufacturing of a phase change memory device that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact. The formed bottom electrode contact exposes a switching device on a semiconductor substrate which the switching device is formed in, forming an insulating layer on a resultant structure of the semiconductor substrate including the bottom electrode contact by using an insulating compound having materials with different atomic sizes, and forming an insulating spacer within the bottom electrode contact hole by selectively etching the insulating layer.

Phase change memory device and fabrication method thereof

Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole.

Methods of manufacturing phase-change memory device and semiconductor device

A phase change memory device is presented that has a lower electrode contact that has a gradient resistance profile ranging from a lower resistive lower end to a higher resistive upper end. The phase change memory device includes a semiconductor substrate, a lower electrode contact, and a phase change pattern. The semiconductor substrate has a switching device. The lower electrode contact is formed on the switching device and has a specific resistance which gradually increases from a lower part to an upper part of the lower electrode contact. The phase change pattern layer is formed on the lower electrode contact.

Phase change memory device capable of satisfying reset current characteristic and contact resistance characteristic

Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer pattern by etching the semiconductor layer pattern; removing the etch stop layer pattern exposed in the recess trench; and forming a gate that fills the recess trench.

Method for fabricating transistor in a semiconductor device utilizing an etch stop layer pattern as a dummy pattern for the gate electrode formation

A method of fabricating a semiconductor device having a gate spacer layer with a uniform thickness wherein a gate electrode layer pattern is formed on a substrate and ion implantation processes of respectively different doses are formed on side walls of the gate electrode layer patterns in respective first and second regions of the substrate. A first gate spacer layer is formed on the gate electrode layer pattern where the ion implantation process is performed. A second gate spacer layer is formed on the first gate spacer layer.

Method of fabricating semiconductor device having gate spacer layer with uniform thickness

A method for forming a capacitor in a semiconductor device is disclosed. The method includes forming a storage node electrode on a semiconductor substrate, forming a dielectric layer having a high dielectric constant on the storage node electrode, depositing a plate electrode on the dielectric layer, thereby forming by-product impurities, and removing by-product impurities remaining on the plate electrode by introducing a hydrogen (H) atom-containing gas onto the semiconductor substrate while depositing a capping layer on the plate electrode.

Method for fabricating capacitor in semiconductor device

Disclosed herein is a method for fabricating a semiconductor memory device that can prevent oxidation of bit lines when forming an interlayer dielectric for isolating the bit lines. The bit line is formed on a semiconductor substrate where an underlying structure is formed. A silicon on dielectric (SOD) layer is formed on the resulting structure where the bit line is formed. A heat treatment can be performed on the SOD layer with a partial pressure ratio of water vapor (HO) to hydrogen (H) in a range of about 1&#xd7;10to about 1.55 at a temperature in a range of about 600&#xb0; C. to about 1,100&#xb0; C.

Growing community of inventors

Icheon-si, South Korea

Hye Jin Seo