Samsung Electronics Co., Ltd.

Hye-jin Kim

Kwang-Jin Lee

Woo-Yeong Cho

Du-Eung Kim

Hyun-Woo Lee

Soon-kyo Hong

Ji-Hwan Kim

Young-Hwan Choi

Seok-chan Lee

Hong-Sik Park

Ju-hyun Kim

Kyung-Man Kim

Dong-Gon Park

Hyun-Bae Kim

Sang-Woo Pae

Ki-Won Lim

Sang-Ho An

Ho-jin Kweon

Chan-hee Park

Chang-han Choi

Mu-hui Park

Sung-hoon Chun

Kyong-Taek Lee

Kae-dong Baek

June-Kyun Park

A voltage generator includes a pulse circuit and a slope circuit. The pulse circuit is to apply voltages of three different levels to an output terminal and the slope circuit is to apply a slope voltage to the output terminal. The slope circuit includes an inductor to take current out of a capacitive load connected to the output terminal.

Voltage generator, voltage waveform generator, semiconductor device manufacturing apparatus, voltage waveform generation method, and semiconductor device manufacturing method

A system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example and may identify a MOS transistor operating with its drain voltage higher than its gate voltage in the circuit. The design system and method may substitute a smaller transistor, having a high-k dielectric layer, for the original transistor in the circuit design.

Circuit design system and semiconductor circuit designed by using the system

Semiconductor packages including stacked semiconductor chips are provided. The semiconductor packages may include first semiconductor chips and a second semiconductor chip that are stacked sequentially on a board. The semiconductor packages may also include a wiring layer on the memory chips and the wiring layer may include redistribution patterns and redistribution pads. Each of the memory chips may include a data pad. The data pads of the first semiconductor chips may be electrically connected to the board via the second semiconductor chip, some of redistribution patterns, and some of redistribution pads.

Semiconductor package including stacked semiconductor chips and a redistribution layer

A PRAM includes a memory cell array of phase change memory cells, and a write circuit receiving an externally provided first voltage and supplying a write pulse for writing data to the memory cells in a normal operation mode. The write circuit also receives an externally provided second voltage higher than the first voltage and supplies a firing pulse to at least one firing-failed phase change memory cell.

PRAM and method of firing memory cells

Provided are a method of and an apparatus for automatically setting a channel to achieve channel synchronization between a transmitter and a receiver in a wireless transceiver system. The transmitter stores information about a channel tuned according to an initial channel number, transmits a message indicating a completion of the channel information storage to a receiver, and transmits a next channel number in response to a message confirming the completion of a channel information storage performed in the receiver. The receiver receives a tuned channel number and the message indicating the completion of the channel information storage in sequence from the transmitter, stores channel information corresponding to the received tuned channel number, transmits the message confirming the completion of the channel information storage to the transmitter, and waits for the next channel number to be received from the transmitter.

Method and apparatus for setting channels automatically in wireless transceiver system

A method of operating a phase change random access memory (PRAM) device comprises performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.

Phase change random access memory device and related methods of operation

A semiconductor memory device comprises a memory cell array comprising memory cells of a first type. The memory cell array performs write and read operations in response to signals designed for the operation of a memory cell array comprising memory cells of a type other than the first type.

Semiconductor memory device and memory system including semiconductor memory device

There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.

Bias voltage generator and method generating bias voltage for semiconductor memory device

A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.

Phase change memory devices and systems, and related programming methods

A method for fabricating a porous composite oxide is provided. The method includes the steps of: (a) slowly mixing a solution including a silicon oxide source and a solution including an aluminum oxide source; (b) adding hydrochloric acid to the mixed solution prepared in said step (a) to obtain a sol; and (c) adding sodium hydroxide to said sol, reacting the obtained resultant at room temperature for 30 minutes to 12 hours, and drying the resultant. The porous composite oxide has an abundance of fine pores and the distribution of pore size is relatively uniform, so that the porous composite oxide is suitable for a carrier.

Growing community of inventors

Gangnam-gu, South Korea

Hye-jin Kim