Xilinx, Inc.

Hy V Nguyen

Richard C Li

Patrick J Crotty

Ting Lu

Bradley L Taylor

Hassan K Bazargan

William Edward Allaire

Shashank Bhonge

Derek R Curd

Gubo Huang

Sholeh Diba

Sandeep Dutta

Andy T Nguyen

Napoleon W Lee

Shankar Lakkapragada

Wei-Yi Ku

Scott S Nance

An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

Integrated circuit with programmable circuitry and an embedded processor system

An integrated circuit can include a processor system configured to execute program code, wherein the processor system is hard-wired. The IC also can include programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system and can be configured to implement a power off procedure under the control of the processor system.

Power management within an integrated circuit

A low-voltage output circuit configurably providing a bus-hold function and a weak pull-up function, while having only transitory leakage current through the circuit regardless of the voltage level on the pad. Thus, the output circuit can be used in low-voltage devices that interface with higher-voltage devices without paying the penalty of increased leakage current. One embodiment of the invention includes a circuit output node coupled to a configurable weak pull-up circuit, a configurable bus hold circuit, and a configurable leakage prevention circuit. The configurable circuits are controlled by configuration signals that determine which circuits are active. One embodiment is implemented as a portion of a programmable logic device (PLD), and the configuration signals are programmed into configuration memory cells as part of the configuration of the PLD.

Configurable bus hold circuit with low leakage current

Output circuits that provide compatibility with various input and output voltage levels without sacrificing performance. A pull-up on an output terminal is gated by an internal node, and the invention encompasses various circuits and means for placing a data input signal on this internal node. One embodiment includes a level shifter on the data input path, while also providing an alternative path through the output circuit that bypasses the level shifter. When the input data value goes high, the alternative path quickly places an attenuated high value on the internal node. The level shifter then becomes active and raises the voltage on the internal node to the output power high level, ensuring that the output pull-up is completely off.

High-speed output circuit with low voltage capability

An output driver on an integrated circuit (IC) includes at least one transistor that has a thicker gate oxide than other standard transistors in the IC. In one embodiment, the output driver includes two pull-up transistors. A first pull-up transistor has a thicker gate oxide than standard transistors on the IC to provide a wide range of output voltages on the pad. A second pull-up transistor has a standard, i.e. thin, gate oxide thickness to ensure a fast low-to-high voltage transition on the pad. The other transistors in the output driver have standard gate oxide thicknesses. Illustrative thicknesses include 150 Angstroms for the first pull-up transistor and 50 Angstroms for the second pull-up transistor.

Output driver circuit using thin and thick gate oxides

A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. The interface circuit includes an impedance control circuit, an output buffer, an input buffer, an isolation circuit, and a pullup protection circuit. The output buffer includes a pullup transistor and a pulldown transistor for applying an output signal to an I/O pad. When a high voltage (i.e., higher than the internal voltage of the interface circuit) is applied to the I/O pad, the pullup protection circuit drives the gate of the pullup transistor to the high I/O pad voltage to ensure that no current flows to the positive supply voltage. Also, the isolation circuit couples the high I/O pad voltage to the body (well) of the pullup transistor to prevent leakage current through parasitic diodes formed by the pullup transistor.

Simplified 5V tolerance circuit for 3.3V I/O design

An input/output (I/O) circuit for transmitting output signals on or receiving input signals from an I/O terminal of an integrated circuit device, such as a Programmable Logic Device (PLD). The I/O circuit includes pull-up and pull-down transistors for generating output signals on the I/O terminal in an output mode, and an isolation transistor for limiting the voltage level transmitted to the pull-up transistor from the I/O terminal in an input mode. The isolation transistor is formed with a thicker gate oxide and a longer channel length than that of the pull-up and pull-down transistors, thereby allowing the isolation transistor to withstand voltages greater than Vcc of the PLD without damage. The isolation transistor is controlled using a charge pump provided on the PLD for programming non-volatile memory cells (e.g., EPROM, EEPROM or flash EPROM cells). The isolation transistor is produced during the same process steps used to produce high voltage transistors associated with the non-volatile memory cells.

Low-voltage input/output circuit with high voltage tolerance

An output driver circuit including a first path from an output pad to ground through a first switch, and a second path from the output pad to ground through series-connected second and third switches. The first switch is directly connected to a pull-down signal source, and one of the second and third switches is connected to the pull-down signal source through a one-shot circuit. In a pull-up state, the first and second switches are opened, and the one-shot circuit generates a stabilized output signal which closes the third switch. When the output driver circuit switches to a pull-down state, the first switch is closed, thereby connecting the output pad to ground via the first path. The signal change also closes the second switch. In addition, due to a propagation delay of the second signal through the one-shot circuit, the third switch initially remains closed, thereby also connecting the output pad to ground via the second path. The one-shot circuit then opens the third switch before the output pad fully discharges. Subsequently, the one-shot circuit returns to its stabilized state and closes the third switch, thereby connecting the substantially fully discharged output pad to ground through both the first and second paths.

Output driver with reduced ground bounce

Problems associated with excessive crowbar current due to input signal transitions at a buffered programmable interconnect point are solved by inserting a transistor switch between power and ground. The inserted switch is in series with the input buffer and is controlled by a memory cell which also controls the pass/no-pass state of the interconnect. An OFF inserted switch blocks current that flows during switching when the memory cell output causes a no-pass state of the interconnect.

Programmable interconnect point having reduced crowbar current

A memory system having a single-sided memory cell, a first voltage supply terminal and a control circuit is provided. The single-sided memory cell has a first node and a second node. Data values are written to the memory cell by selectively applying data signals to the first node or the second node, and data values are read from the memory cell from the second node. The control circuit is coupled to receive a data signal having one of a first state and a second state. The control circuit couples the first node of the memory cell to the first voltage supply terminal when the data signal is in the first state, thereby writing a first data value to the memory cell. The control circuit couples the second node of the memory cell to the first voltage supply terminal when the data signal is in the second state, thereby writing a second data value to the memory cell. Because the first voltage supply terminal is used to write both the first and second data values to the memory cell, problems associated with inadequate write voltages are eliminated by appropriate selection of the first supply voltage.

Single-sided RAM cell and method of accessing same

A selectively decoupled latch circuit used for latching a signal. The circuit contains an input line for accepting an input signal to the circuit. A latch is connected to the input line for latching the input signal. A transfer gate is also connected to the input line and latch for transferring the input signal to the latch according to a clock signal. A transistor is connected in a series with a feedback loop associated with the latch. The transistor selectively decouples the feedback path according to the clock signal. By selectively decoupling the feedback path, it is easier for a new input signal to become latched because contention between a prior latched signal versus the new input signal is minimized. An output line is connected to the latch for outputting a latched signal.

Selectively decoupled I/O latch

Propagation delay along a signal path in a programmable logic device is reduced by providing improved switching and buffering along the device signal path. Such improvement is achieved by providing a separate buffer for each signal path leading from a given device input pad. In this manner, the buffer is smaller without increasing net power consumption. Improved output drivers are also provided in which device sizes are optimized to sink/source larger amounts of current, thereby improving device speed. A feedback arrangement, including a bootstrap device, provides a path that augments the current provided within the output buffer, thereby assisting a low to high signal transition. An improved OR gate is also provided that precharges a gate output line to ensure fast state transition, while eliminating the need for complementary gate switching logic.

Fast signal path for programmable logic device

In an EPLD, a feedback switching circuit is provided on a feedback line connected between a macrocell output line and a interconnect matrix wordline, the switching circuit including a memory element and a switch for passing a macrocell output signal from the output line to the interconnect matrix wordline when the memory element is in a first state, and for blocking the macrocell output signal when the memory element is in a second state. This prevents coupling noise in the interconnect matrix because unnecessary feedback signals are prevented from entering the interconnect matrix. In another embodiment, a method is provided in which unused macrocells produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by a multiple concurrent switching event. In another embodiment, a sense amplifier is provided in which an EPROM shields coupling between wordlines and bitlines in an interconnect matrix.

Method and apparatus for reducing coupling switching noise in

A CMOS buffer includes an input inverter, and a pull-up circuit coupled to the input inverter. The pull-up circuit provides an additional, temporary, signal pull-up on the output terminal of the input inverter during a high to low signal transition on its input terminal. The pull-up circuit includes a means for creating a signal delay. In one embodiment, the means for creating a signal delay includes a second and third inverter in series, the second inverter receiving an output signal from the input inverter. The pull-up circuit further includes two transistors for transferring a high signal to an output line of the input inverter. One transistor is controlled by a signal transferred by the means for creating a delay. The other transistor is controlled by an input signal to the input inverter. This pull-up circuit configuration ensures that the signal transition from low to high is substantially equal to the signal transition from high to low on the output line of the input inverter. The input inverter is then coupled to a driving circuit inverter to provide a CMOS buffer configuration.

Growing community of inventors

San Jose, CA, United States of America

Hy V Nguyen