Nvidia Corporation

Hwong-Kwo (Hank) Lin

Charles Chew-Yuen Young

Ge Yang

Guoqing Ning

Beibei Ren

Apparatuses and methods are provided for a self-timed dynamic sense amplifier flop circuit, wherein a pulse generating circuit may be adapted to generate at least a first logic signal based, at least in part, on a first evaluation node signal, and a discharge path circuit comprising at least a first transistor within a first stack of transistors may be operatively responsive to the first timing signal.

Self-timed dynamic sense amplifier flop circuit apparatus and method

One embodiment of the present invention sets forth a twelve transistor static random access memory storage cell that provides two write ports and three read ports. The write word line operates at twice the clock frequency. The write bit lines are differential to provide high-performance writes. Each read word line operates at the clock frequency. Single-ended read bit lines are used to provide read performance comparable to write performance. The resulting storage cell only requires four horizontal word lines and five vertical bit lines, enabling very dense, yet high-performance designs.

2-write 3-read SRAM design using a 12-T storage cell

One embodiment of the present invention sets forth a high-speed single-ended memory read circuit that overcomes performance limitations of conventional single ended memory read circuits. A bit line keeper control mechanism for the high-speed single-ended memory read circuit is disclosed that automatically configures the bit line keeper for high-speed operation or low-speed operation, based on the frequency of a system clock. In high-speed operation, the bit line keeper is disabled, thereby eliminating short-circuit currents related to the bit line keeper and increasing the read performance of the single-ended memory read circuit. In low-speed operation, the bit line keeper is periodically disabled by a timer circuit to enable efficient read or write operations. Subsequent to the read or write operation, the bit line keeper is enabled to preserve state on the bit lines. By selectively enabling the bit line keeper, high-speed performance is improved while preserving correct function at low speeds.

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Palo Alto, CA, United States of America

Hwong-Kwo (Hank) Lin