Samsung Electronics Co., Ltd.

Hwi-Taek Chung

Jong-Min Park

Min-Sung Kim

Yoon-Kyung Choi

Jin-Bong Kim

Eung-Man Kim

Young-Ho Lim

Seung-Keun Lee

Ki-Hong Kim

Myong-Jae Kim

Young-Joo Lee

San-ho Byun

Do-Kyung Kim

Kang-Doeg Suh

Cha-Dong Kim

Yeon-Bae Chung

Seoung-Keun Lee

Provided are a touch processor for performing active protection, a touch display driver integrated circuit (DDI) chip including the touch processor, and a method of operating the touch processor. The touch processor for driving a touch panel including a sensing cell includes a driving circuit configured to provide a driving signal to the touch panel, and a capacitance controller. The capacitance controller is configured to generate a switch control signal for controlling a switch connected to a sensing unit included in the sensing cell, and a compensation signal having a different waveform than the driving signal, so as to reduce a value of an ambient capacitance component of the sensing cell.

Touch processor, touch display driver integrated circuit chip including touch processor, and method of operating touch processor

A touch sensing apparatus includes a plurality of touch sensors provided in a touch panel and a switching unit for transmitting sensing signals per column or row of the touch sensors through a single line to a touch controller.

Touch sensing apparatus, touch sensing method, touch sensing system, and display system using the same

An integrated circuit supporting a first interface and a second interface and an integrated circuit card having the same includes the first interface capable of communicating with a first host, the second interface communicating with a second host, and a control block. The control block activates the second interface when a voltage level of a contact that the second host can be connected is in a first state at a first-occurring timepoint between a reference timepoint and a state transition timepoint of an external reset signal output from the first host, and deactivates the second interface when the voltage level of the contact is in a second state. The integrated circuit card has the integrated circuit built in.

Integrated circuit having a plurality of interfaces and integrated circuit card having the same

A semiconductor memory device controlling an output voltage level of a high voltage generator in response to a variation of temperature has a high voltage generator that provides a high voltage higher than a power source voltage through an output terminal, generates a temperature detection signal obtained by sensing a variation of a diode current based on a temperature variation, and adjusts a voltage level of the output terminal in response to the temperature detection signal. The device is able to automatically control an output voltage or current of the high voltage generator.

Semiconductor memory device controlling output voltage level of high voltage generator according to temperature variation

A flash memory device provides for a stable source line regardless of bit line coupling during a read operation and regardless of loading effect during a manufacturing process. The flash memory device includes: a plurality of flash memory cells arranged in rows and columns, each of the flash memory cells having a control gate, a source and a drain; a plurality of first, odd-numbered word lines each of which is connected with corresponding control gate of a first set of the flash memory cells; a plurality of second, even-numbered word lines each of which is connected with corresponding control gate of a second set of the flash memory cells; a plurality of bit lines each of which is connected with corresponding a drain of the flash memory cells; and a plurality of selection transistors connected between a source line and a discharge line, the source line being connected to sources of the first and second sets of flash memory cells, the selection transistors comprising the same structure as the first and second sets of the flash memory cells.

Flash memory device with stable source line regardless of bit line coupling and loading effect

A boosting unit comprises a plurality of boosting circuits. Each boosting circuit includes an input driving circuit, a switching circuit, a capacitor circuit, and a precharge circuit. The input driving circuit drives a corresponding external boosting signal. The switching circuit transfers either a power supply voltage, a ground voltage, or a boosting signal from one of the other boosting circuits to the capacitor circuit under the control of the corresponding external boosting signal. The capacitor circuit boosts up a boosting node, which has been precharged to a power supply voltage level by the precharge circuit, to predetermined voltage level higher than an input voltage level. The boosting circuits are connected together in series and simultaneously carry out a boosting operation. The boosting unit therefore provides a desired boosted voltage level at high speed.

Boosting circuit of semiconductor memory device

The invention provides decoder circuits for selecting a word line in a semiconductor memory device which comprises a plurality of memory cell sectors including a plurality of word lines and bit lines and a plurality of memory cells which each is electrically erasable and programmable. The decoder circuits comprise a pull-up and pull-down transistors connected to global word lines which are connected to the word lines via connecting means, the decoder circuits turning on pull-down transistors before a high voltage according to an operation mode is supplied to one selected from the global word lines and pre-charging the gates of the pull-up transistors to the high voltage. The invention enables the decoder circuits to supply the word line drive voltage to the global word lines connected to memory cells by using the self-boosting method to thereby reduce the boosting load.

Row decoder for a nonvolatile memory device

A nonvolatile semiconductor memory device is provided, which supports an erase verify operation mode to determine whether an erased memory cell is lower than a maximal threshold voltage (e.g., 3V), and a test verify operation mode to determine whether the erased memory cell has a progressive fail characteristic. Once the memory device enters the test verify operation mode, a wordline voltage to be applied to a memory cell and a reference wordline voltage to be applied to a reference cell are generated. The wordline and reference wordline voltages generated in the test verify operation mode are set to be higher than those generated in the erase verify operation mode. This makes it possible to compare current flowing through the memory cell and reference cell at more than one level and to check a memory cell for a progressive (or potential) failing characteristic.

Flash memory device capable of checking memory cells for failure characteristics

A memory device includes first, second, and third discharging units, which are connected to a negative voltage node, for discharging the negative voltage to a ground voltage through three steps which are sequentially conductive. The first discharging unit discharges the negative voltage in response to a first signal and a second signal. It does so when the negative voltage is a first voltage level. The second discharging unit discharges the negative voltage in response to the second signal and a third signal. It does so when the negative voltage is a second voltage level. The third discharging unit discharges the negative voltage in response to a fourth signal and a fifth signal. It does so when the negative voltage is a third voltage level.

Internal power supply voltage generating circuit and the method for controlling thereof

A nonvolatile semiconductor device which includes a word line, a bit line, and a memory cell connected to the word line and the bit line, also has a word line driving circuit for driving the word line with a word line voltage supplied in response to a shut off signal in accordance with each mode of operation, and a circuit for generating the shut off signal during each mode of operation. The circuit generates the shut off signal which has a power supply voltage when the word line voltage is higher than the power supply voltage, and has the word line voltage when the word line voltage is less than the power supply voltage.

Nonvolatile semiconductor memory device with a level shifter circuit

A semiconductor memory device is provided which comprises a mat having a plurality of sectors for storing information of data; and a redundancy circuit for generating a plurality of redundancy selection signals to be applied in common to the sectors when the enable fuse element is open-circuited. Each of the sectors comprises a main memory cell array plural input/output blocks, each of which corresponds to the input/output pins and has two bit and the redundancy memory cell array divided into two redundant bit segments, each of which has two redundant columns of redundant memory cells. Each sector further comprises a first column selector for selecting one of the main columns of each bit segment in response to first column address signals; a second column selector for selecting one of the two redundant columns of each redundant bit segment in response to one of the first column address signals; and a third column selector for selecting one of the two bit segments in each input/output block and one of the two redundant bit segments in response to second column address signals. Furthermore, each sector has a plurality of sense amplifiers for sensing and amplifying stored data in corresponding main column and redundant column thus selected; and a plurality of multiplexers each for receiving outputs from a first corresponding sense amplifier and from the second sense amplifier and selecting one of the outputs thus received in response to a corresponding redundancy selection signal.

Semiconductor memory device with a column redundancy occupying a less

Disclosed herein is a nonvolatile semiconductor memory device which comprises a voltage level sensing circuit for detecting whether a word line voltage and a bit line voltage are boosted up to their target levels for a program operation. When the voltages are boosted up to the target levels, the voltage level sensing circuit generates a pulse signal for indicating that the word line and bit line voltages are sufficiently boosted up to the target levels. The nonvolatile semiconductor memory device realized according to this scheme can reduce a program time when it is implemented using the higher power supply voltage. Therefore, optimized program time of the memory device according to the present invention is secured.

Nonvolatile semiconductor memory device capable of optimizing program

A semiconductor memory device is provided which comprises a mat having a plurality of sectors for storing information of data; and a redundancy circuit for generating a plurality of redundancy selection signals to be applied in common to the sectors when the enable fuse element is open-circuited. Each of the sectors comprises a main memory cell array and the redundancy memory cell array divided into two redundant bit segments, each of which has two redundant columns of redundant memory cells. Each sector further comprises a first column selector for selecting one of the main columns of each bit segment in response to first column address signals; a second column selector for selecting one of the two redundant columns of each redundant bit segment in response to one of the first column address signals; and a third column selector for selecting one of the two bit segments in each input/output block and one of the two redundant bit segments in response to second column address signals. Furthermore, each sector has a plurality of sense amplifiers for sensing and amplifying stored data in corresponding main column and; redundant column thus selected; and a plurality of multiplexers each for receiving outputs from a first corresponding sense amplifier and from the second sense amplifier and selecting one of the outputs thus received in response to a corresponding redundancy selection signal.

A nonvolatile semiconductor memory device which comprises a memory cell array having a plurality of memory blocks each divided into a plurality of segments, each of which has a plurality of word lines, a plurality of bit lines arranged to intersect the word lines, and a plurality of memory cells connected to the word lines and the bit lines. The device has means for decoding segment select signals to generate a decode signal that selects one of the segments, and means connected to a first power node, for receiving word line select signals to select one of the word lines in the selected segment to output a first voltage applied to the first power node. In the nonvolatile semiconductor memory device, furthermore, a word line driver, which is connected to a second power node, applies the first voltage to the selected word line during read, write, and test modes of operation, and applies a second voltage supplied to the second power node to the selected word line during an erase mode of operation, in response to the decoded signal from the decoding means.

Growing community of inventors

Kyunggi-do, South Korea

Hwi-Taek Chung