Pep Innovation Pte. Ltd.

Advanpack Solutions Pte Ltd.

Advanced Systems Automation Limited

Hwee Seng Jimmy Chew

Dingwei Xia

Shoa Siong Raymond Lim

Senthil Kumar Munirathinam

A wafer-level buffer layer is disclosed. The wafer-level buffer layer is configured to prevent cracking and chipping the back-end-of-line (BEOL) dielectric during wafer singulation process. The wafer-level buffer layer is a composite wafer-level buffer layer with a vibration damping agent. The vibration damping agent includes a polymer-based base layer with fillers. The damping agent absorbs or dampens the vibration of the saw blade during dicing to prevent cracking and chipping of the BEOL dielectric.

Semiconductor device with buffer layer

The present disclosure discloses a method of packaging a chip and a chip package structure. The method of packaging the chip includes: forming a protective layer on a front surface of a chip to be packaged; mounting the chip to be packaged formed with the protective layer on the front surface on a first carrier, the back surface of the chip to be packaged facing upwards and a front surface thereof facing towards the first carrier; forming a first encapsulation layer, the first encapsulation layer being formed on the back surface of the chip to be packaged and the exposed first carrier; and detaching the first carrier to exposed the protective layer. In the present disclosure, when the chip to be packaged is mounted on the carrier after the protective layer is formed on the front surface thereof; and then the first encapsulation layer is formed on the chip to be packaged, the encapsulation material can be prevented from permeating to the gap between the chip to be packaged and the carrier and thereby damaging the circuit structure and/or the bonding pad on the chip to be packaged.

Method of packaging chip and chip package structure

The present disclosure discloses a method of packaging a chip and a chip package structure. The method of packaging the chip includes: forming a protective layer on a front surface of a chip to be packaged; mounting the chip to be packaged formed with the protective layer on the front surface on a first carrier, the back surface of the chip to be packaged facing upwards and a front surface thereof facing towards the first carrier; forming a first encapsulation layer, the first encapsulation layer being formed on the back surface of the chip to be packaged and the exposed first carrier; and detaching the first carrier to exposed the protective layer. In the present disclosure, when the chip to be packaged is mounted on the carrier after the protective layer is formed on the front surface thereof, and then the first encapsulation layer is formed on the chip to be packaged, the encapsulation material can be prevented from permeating to the gap between the chip to be packaged and the carrier and thereby damaging the circuit structure and/or the bonding pad on the chip to be packaged.

The present disclosure discloses a method of packaging a chip and a chip package structure. The method of packaging the chip includes: mounting at least one chip to be packaged on a carrier, a back surface of the chip to be packaged facing upwards and an active surface facing towards the carrier; forming a sealing layer, the sealing layer being at least wrapped around the at least one chip to be packaged; forming a first encapsulation layer, wherein the first encapsulation layer covers the entire carrier for encapsulating the at least one chip to be packaged and the sealing layer; detaching the carrier to expose the active surface of the at least one chip to be packaged; and completing the packaging by a rewiring process on the active surface of the at least one chip to be packaged. The active surface of the chip to be packaged is mounted on the carrier, and the chip to be packaged is fixed on the carrier at a predetermined position by the sealing layer, so that the position of the chip to be packaged in the subsequent process is not easily moved.

The embodiment of the present disclosure discloses a method of packaging a chip and a chip package structure. the method of packaging the chip includes: mounting at least one chip to be packaged and at least one electrically conductive module on a carrier, wherein the at least one chip to be packaged has a back surface facing upwards and an active surface facing towards the carrier, and the at least one electrically conductive module is in the vicinity of the at least one chip to be packaged; forming a first encapsulation layer, wherein the first encapsulation layer covers the entire carrier for encapsulating the at least one chip to be packaged and the at least one electrically conductive module; detaching the carrier to expose the active surface of the at least one chip to be packaged and a first surface of the at least one electrically conductive module; and completing the packaging by a rewiring process on the active surface of the at least one chip to be packaged and the first surface of the at least one electrically conductive module. The present disclosure reduces the difficulty of packaging a chip by mounting the active surface of a chip to be packaged and an electrically conductive module on a carrier and thus saves the cost of packaging.

A semiconductor structure and a method of fabricating the same. The semiconductor structure comprises: a layer element, one or more supporting elements disposed on a first surface of the layer element, and one or more anchoring elements disposed within the layer element and connected to the one or more supporting elements to couple the one or more supporting elements to the layer element to strengthen the layer element.

Semiconductor structure and method of fabricating the same

Mold pieces (and) for molding a layer of mold compound on the interconnect side of a bumped semiconductor wafer () include a primary cavity () and secondary cavities () into which excess mold compound from the primary cavity () flows. The secondary cavities () include a plunger () that asserts a predetermined backpressure that is equal to a desired mold compound pressure on the mold compound during molding. As most of the excess mold compound in the primary cavity () is forced to flow into the secondary cavities (), this advantageously leaves a relatively thin layer of mold compound on the semiconductor wafer (), which can then be removed, for example by grinding in a relatively short time. Mold piece () further comprises a movable cavity bar () that can be moved away from mold piece () after molding and be cooled to detach the molded substrate that adheres to the cavity bar.

Growing community of inventors

Singapore, Singapore

Hwee Seng Jimmy Chew