Advanpack Solutions Pte Ltd.

Hwee-Seng Jimmy Chew

Shoa-Siong Lim

Chee Kian Ong

Kian-Hock Lim

Oviso Dominador Jr Fortaleza

Bin Chichik Abd Razak

Kee Kwang Lau

Oviso Dominador Fortaleza, Jr

Chee-Kian Ong

A manufacturing method of a semiconductor package includes the following steps. Firstly, a conductive carrier is provided. Then, a first conductive layer is formed on a lower surface of the conductive carrier. Then, a second conductive layer is formed on a lower surface of the first conductive layer, wherein the second conductive layer and the first conductive layer together constitute a conductive structure. Then, an electrical component is disposed on the lower surface of the first conductive layer. Then, a first package body encapsulating the first conductive layer, the second conductive layer and the electrical component but not covering an edge of the lower surface of the conductive carrier is formed. Then, a portion of the first package body is removed. Then, partial material of the conductive carrier is removed, such that a reserved part of the conductive carrier forms a ring-shaped conductive structure.

Manufacturing method of semiconductor package

A manufacturing method of a package substrate is provided. A conductive substrate is provided. A first photoresist layer is patterned to form first openings. A first conductive layer is formed in the first openings. A second photoresist layer is patterned to form second openings. A second conductive layer contacting the first conductive layer is formed in the second openings. The first and second photoresist layers are removed. A dielectric layer covers the first, second conductive layers and a portion of the conductive substrate. A portion of the dielectric layer is removed. A third photoresist layer is patterned to form a third opening. A portion of the conductive substrate is removed to form a fourth opening. The third photoresist layer is removed. A fourth photoresist layer is patterned to form a fifth opening. A bonding pad is formed in the fifth opening. The fourth photoresist layer is removed.

Manufacturing method of package substrate and package manufacturing method of semiconductor device

A substrate structure, a semiconductor package and a manufacturing method of semiconductor package are provided. The substrate structure comprises a conductive structure, an electrical component, a package body and a ring-shaped conductive structure. The conductive structure comprises a first conductive layer and a second conductive layer. The first conductive layer has a lower surface. The second conductive layer and the electrical component are formed on the lower surface of the first conductive layer. The package body encapsulates the conductive structure and the electrical component and has an upper surface. The ring-shaped conductive structure surrounds the conductive structure and the electrical component and is disposed at the edge of the upper surface of the package body to expose the conductive structure.

Substrate structure, semiconductor package device, and manufacturing method of semiconductor package

A manufacturing method of a substrate structure is provided. The method includes the following steps. Firstly, a conductive carrier is provided. Then, a first metal layer is formed on the conductive carrier. Then, a second metal layer is formed on the first metal layer. Then, a third metal layer is formed on the second metal layer, wherein each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface, the first surface of the third metal layer is connected to the second surface of the second metal layer, the surface area of the first surface of the third metal layer is larger than the surface area of the second surface of the second metal layer, and the first metal layer, the second metal layer and the third metal layer form a conductive structure.

Manufacturing method of substrate structure having embedded interconnection layers

A semiconductor package includes a dielectric layer, a plurality of traces, a plurality of electrical pads, a plurality of studs and at least a semiconductor device. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The traces are disposed in the dielectric layer and are exposed on the second dielectric surface. The electrical pads are disposed on the first dielectric surface. The studs are disposed in the dielectric layer and are exposed on the first dielectric surface. The studs are electrically connected to the traces and the electrical pads. The semiconductor device is disposed on the second dielectric surface and electrically connected to the traces.

Semiconductor package

A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.

Semiconductor device carrier for fine pitch packaging miniaturization and manufacturing method thereof

A package substrate including a dielectric layer, a first conductive layer, a second conductive layer and a bonding pad is provided. The dielectric layer has a top surface and a bottom surface. The first conductive layer is embedded into the dielectric layer, and a first surface of the first conductive layer is exposed from the top surface and has the same plane with the top surface. The second conductive layer is embedded into the dielectric layer and contacts the first conductive layer, and a second surface of the second conductive layer is exposed from the bottom surface and has the same plane with the bottom surface. The bonding pad is partially or completely embedded into the first conductive layer and the dielectric layer, so that the periphery of the bonding pad is confined within a cavity by the sidewalls of both the first conductive layer and the dielectric layer.

Package carrier, package carrier manufacturing method, package structure for semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.

Chip and manufacturing method thereof

A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad.

Manufacturing method of forming an etch-back type semiconductor package with locking anchorages

A substrate structure includes first, second and third metal layers embedded in a dielectric layer between its opposite upper first and lower second surfaces. The entire upper surface of the first metal layer is exposed on the first surface of the dielectric layer, the entire lower surface of the third metal layer is exposed on the second surface of the dielectric layer, and the second metal layer is disposed between the first metal layer and the third metal layer, wherein the area of the third metal layer is larger than the area of the second metal layer.

Substrate structure, semiconductor package device, and manufacturing method of substrate structure

A semiconductor element that includes a forsy patterned conductive layer, a second pattern conductive layer and an insulating layer. The first surface of the second patterned conductive layer is connected to a second surface of the first patterned conductive layer. The insulating layer includes at least one space on a second surface thereof. The first patterned conductive layer and the second patterned conductive layer are embedded in the insulating layer between a first surface and a second surface thereof, the first surface of the first patterned conductive layer is entirely exposed on a first surface of the insulating layer, a second surface of the second patterned conductive layer is entirely exposed on the second surface of the insulating layer, and the space exposes the second surface of the first patterned conductive layer.

Semiconductor element for package miniaturization

The semiconductor device carrier comprises a conductive carrier, a dielectric layer, a conductive trace layer, a conductive stud layer and the plating conductive layer. The conductive carrier comprises at least one cavity. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The conductive trace layer disposes in the dielectric layer and is exposed on the second dielectric surface. The conductive stud layer disposes in the dielectric layer and is exposed on the first dielectric surface, wherein the conductive stud layer is electrically connected to the conductive trace layer. The plating conductive layer is disposed on the first dielectric surface and the exposed conductive stud layer. The cavity exposes the conductive trace layer and the dielectric layer.

Semiconductor device carrier and semiconductor package using the same

Etch-back type semiconductor package, substrate and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed on the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is more than 1.2 times the second dimension. The top part is composed of solder and will melt under a pre-determined temperature. The pillar part will not melt under the pre-determined temperature.

Interconnections for fine pitch semiconductor devices and manufacturing method thereof

A package structure including a first semiconductor element, a second semiconductor element, a semiconductor interposer and a substrate is provided. The first semiconductor element includes multiple first conductive bumps. The second semiconductor element includes multiple second conductive bumps. The semiconductor interposer includes a connection motherboard, at least one signal wire and at least one signal conductive column. The signal wire is disposed on the connection motherboard. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps respectively. The signal conductive column is electrically connected to the signal wire. The substrate is electrically connected to the signal conductive column. The first and the second semiconductor elements have the same circuit structure. The substrate of the package structure can simultaneously form a signal communication path with the first and the second semiconductor element respectively.

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Singapore, Singapore

Hwee-Seng Jimmy Chew