Advanpack Solutions Pte Ltd.

Pep Innovation Pte. Ltd.

Pyxis Cf Pte. Ltd.

Orion Systems Integration Pte Ltd

Microfits & Methods Pte. Ltd.

Hwee Seng Chew

Shoa Siong Lim

Amlan Sen

Chee Kian Ong

Kian Hock Lim

Wai Hoe Lee

Qing Feng Guan

Siew Wen Lee

Kin Fei Chooi

Li Jiang Huang

A die bonding apparatus having: a carrier support unit having at least one support element defining a supporting plane and a carrier holder operable to support the carrier panel on a side of the supporting plane with the carrier panel being parallel to the supporting plane, a wafer feed unit having a wafer holder operable to hold a diced wafer in a manner so as to space the diced wafer apart from the supporting plane defined by the at least one support element of the carrier support unit and orient the diced wafer with an exposed surface of the diced wafer facing the side of the supporting plane to which the carrier panel is supported, and a die transfer module disposed between the carrier support unit and the wafer feed unit, the die transfer module operable to transfer a die from the diced wafer to the carrier panel.

Apparatus and method for bonding a plurality of dies to a carrier panel

The present disclosure discloses a semiconductor structure having an insulating layer disposed on a wafer active surface of a semiconductor wafer for covering the wafer active surface. The insulating layer may be a protective layer in some embodiments and a cover layer in other embodiments. The insulating layer has via openings to expose contact pads for leading out electrical connections. In particular, the via openings are formed by a multi-step etching process (such as a two-step etching process) without damaging the contact pads. The two-step etching process includes a first laser etching process using normal pulse (P) and normal energy to form partial via openings in the cover layer. The second etching process includes either a laser etching process using low P and low E or a plasma etching process. The second etching process avoids damaging the contact pads.

Semiconductor structures with via openings and methods of making the same

The present invention provides a semiconductor substrate () comprising two or more layers of built-up structural layers () formed on a sacrificial carrier (). Each built-up structural layer, comprising a conductor trace layer (,) and an interconnect (), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (). A multi-layer substrate () is then obtained after an outermost conductor trace layer () is formed on the adhesion layer and the carrier () or reinforcing ring () is removed.

Multi-layer substrate for semiconductor packaging

A method for fabricating a flip-chip semiconductor package. The method comprises processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. Processing of the semiconductor chip results in heating of the semiconductor chip to a chip process temperature. The chip process temperature melts solder portions on the bump structures Processing of the substrate results in heating of the substrate to a substrate process temperature. The method comprises spatially aligning the semiconductor chip in relation to the substrate to correspondingly align the bump structures in relation to the bump pads. The semiconductor chip is then displaced towards the substrate for abutting the bump structures of the semiconductor chip with the bond pads of the substrate to thereby form bonds therebetween. A system for performing the above method is also disclosed.

Method for device packaging

A carrier for an integrated circuit package comprises an integral moulding of resilient plastics material and comprising end portions (4) formed on one surface with ribs (7) defining channels (8) for package leads, and interconnected by side wall portions (5) to define a window (9). The package is located on the carrier overlying the window by blending the carrier so that undercut grippers (11) are moved apart to allow the package to pass between them, whereafter the package is gripped when the carrier readopts its normal configuration.

Carrier for an integrated circuit package

Growing community of inventors

Singapore, Singapore

Hwee Seng Chew