Samsung Electronics Co., Ltd.

Hwanyoung Choi

Hyeongmun Kang

Jungmin Ko

Taehyeong Kim

Insup Shin

Woodong Lee

A semiconductor package includes a base structure, a lower semiconductor chip disposed on the base structure, an upper semiconductor chip disposed on the lower semiconductor chip, a connecting structure including a lower pad disposed on the lower semiconductor chip, an upper pad disposed under the upper semiconductor chip, and a connecting bump disposed between the lower pad and the upper pad, a dummy chip disposed on the upper semiconductor chip, an upper adhesive layer including an upper adhesive portion disposed between the upper semiconductor chip and the dummy chip, and an upper protrusion portion disposed at opposite sides of the upper adhesive portion, to surround lower portions of opposite side surfaces of the dummy chip, and a molding layer disposed at opposite sides of the dummy chip, to surround upper portions of the opposite side surfaces of the dummy chip and the upper protrusion portion.

Semiconductor package including a dummy chip

A chip-stacked semiconductor package includes: a base chip having a base through via; a first chip stacked on the base chip in an offset form, wherein the first chip has a first exposed surface and a first through via electrically connected to the base through via; a first molding layer positioned on the base chip and covering a first non-exposed surface, facing the first exposed surface, of the first chip; a second chip stacked on the first chip in an offset form, wherein the second chip has a second exposed surface and a second through via electrically connected to the first through via; and a second molding layer formed on the first chip and covering a second non-exposed surface, facing the second exposed surface, of the second chip.

Growing community of inventors

Hwaseong-si, South Korea

Hwanyoung Choi