Samsung Electronics Co., Ltd.

Hwanyeol Park

Sejin Kyung

Ilwoo Kim

Daewee Kong

Junghwan Lee

Minwoo Lee

Sejun Park

Jeeyong Kim

Dae Wee Kong

Se Jin Kyung

Songyi Baek

Junhyoung Cho

Tae-Min Kim

Jongyoung Park

Yongdeok Lee

Philippe Coche

Youngho Jeung

Kyung Nam Kang

A method of manufacturing a semiconductor device includes preparing a substrate including cell regions and a scribe lane region, forming circuit blocks in the cell regions of the substrate, the substrate including a first surface and a second surface, forming a bias pad on the first surface of the substrate, such that the bias pad is in the scribe lane region of the substrate, bonding a deuterium exchange structure to the second surface of the substrate, implanting deuterium into the deuterium exchange structure using plasma processing, and applying a first voltage to the bias pad, such that the deuterium is diffused from the deuterium exchange structure into the substrate through the second surface of the substrate.

Semiconductor device having deuterium diffused into the substrate and method of manufacturing the same

An apparatus for manufacturing a semiconductor device and a method of manufacturing the apparatus, the apparatus including a heater configured to heat a target, and a coating layer, the coating layer including a ternary material of transition metal (M)-aluminum (Al)-nitrogen (N) represented by the following Chemical Formula:MAlN,  [Chemical Formula]wherein x and y satisfy the following relations: 0<x<1 and y≥1.

Apparatus for manufacturing a semiconductor device and method of manufacturing the apparatus

An integrated circuit device includes: a semiconductor substrate having a cell region and a dummy region outside the cell region, a plurality of gate electrodes and a plurality of insulating layers, in the cell region, extending in first and second directions parallel to a main surface of the semiconductor substrate and alternately stacked in a third direction perpendicular to the main surface of the semiconductor substrate, the first and second directions crossing each other, and a plurality of dummy mold layers and a plurality of dummy insulating layers alternately stacked in the dummy region in the third direction, wherein a carbon concentration of an upper dummy mold layer of the plurality of dummy mold layers is less than a carbon concentration of a lower dummy mold layer of the plurality of dummy mold layers, the lower dummy mold layer being between the upper dummy mold layer and the main surface of the semiconductor substrate.

Integrated circuit device and electronic system including the same

In a method of manufacturing a semiconductor device, a first insulation layer and a first sacrificial layer are alternately and repeatedly formed on a substrate to form a mold layer. A sacrificial layer structure is formed on the mold layer to include an etch stop layer and a second sacrificial layer sequentially stacked. After forming a hard mask on the sacrificial layer structure, the sacrificial layer structure and the mold layer are etched by a dry etching process using the hard mask as an etching mask to form a channel hole exposing an upper surface of the substrate and form a recess on a sidewall of the second sacrificial layer adjacent to the channel hole. A memory channel structure is formed in the channel hole. The first sacrificial layer is replaced with a gate electrode.

Methods of manufacturing a semiconductor device

Provided is a semiconductor device. The semiconductor device includes a wafer; an etch stop layer on the wafer; a lower mold layer on the etch stop layer; an intermediate supporter layer on the lower mold layer; an upper mold layer on the intermediate supporter layer; an upper supporter layer on the upper mold layer; and a hard mask structure on the upper supporter layer, wherein the hard mask structure includes a first hard mask layer on the upper supporter layer and a second hard mask layer on the first hard mask layer, one of the first hard mask layer and the second hard mask layer includes a first organic layer including a SOH containing C, H, O, and N, and the other one of the first hard mask layer and the second hard mask layer includes a second organic layer including an SOH containing C, H, and O.

Semiconductor device including hard mask structure with repeating spin-on hard mask layers

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Seoul, South Korea

Hwanyeol Park