Samsung Electronics Co., Ltd.

Daegu Gyeongbuk Institute of Science and Technology

Hwanjun Lee

Jin Woo Jung

Daehoon Kim

Jinin So

Jonggeon Lee

A processor includes a processing core configured to process each of a plurality of requests by accessing a corresponding one of a first memory and a second memory, a latency monitor configured to generate first latency information and second latency information, the first latency information comprising a first access latency to the first memory, and the second latency information comprising a second access latency to the second memory, a plurality of cache ways divided into a first partition and a second partition, and a decision engine configured to allocate each of the plurality of cache ways to one of the first partition and the second partition, based on the first latency information and the second latency information.

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Daegu-si, South Korea

Hwanjun Lee