Samsung Electronics Co., Ltd.

Hwa-yeal Yu

Dong-Jin Keum

Sung-Woo Moon

Gwang-Yol Noh

Ryotaro Kudo

Hyun-Wook Yoo

Myeong-Lyong Ko

Yu-Seok Ko

A switching regulator switches a current from input direct current (DC) power to generate target DC power. The switching regulator includes: a direct current (DC)-DC converter and a ripple injection circuit. The DC-DC converter is configured to: generate an output voltage at an output terminal based on an input voltage applied to an input terminal, and according to a switching cycle that selectively forms a voltage-down current path or a voltage-up current path based on a comparison between a reference voltage and a voltage sensed at a feedback node; and apply a feedback current from the output terminal to the feedback node. The ripple injection circuit is configured to: generate a pulse current synchronized with the switching cycle; and apply the pulse current to the feedback node.

Switching regulators

A bi-directional voltage positioning circuit includes a voltage to current converter, a current mirror circuit and a switch. The voltage to current converter converts a sensing voltage to a first current, and the sensing voltage is sensed based on a current flowing through an output coil connected between a switching node and an output node. The current mirror circuit mirrors the first current to generate a second current and a third current, the second current is N times greater than the first current, the third current is M times greater than the first current, and N and M are real numbers greater than zero. The switch provides a feedback node with one of the second current and third current in response to a switching control signal, and an output voltage of the output node is divided at the feedback node.

Bi-directional voltage positioning circuit, voltage converter and power supply device including the same

A sigma-delta modulator (SDM) includes a delay circuit and an operation circuit. The delay circuit generates multiple clock signals with different delays. The operation circuit includes a plurality of operation stages that operate with timing according to all of the clock signals for high-order sigma-delta modulation. Thus, noise may be dispersed for minimizing noise coupling. The SDM is used to particular advantage within a fractional-N phase-locked loop.

Sigma-delta modulation with minimized noise and fractional-N phase-locked loop including the same

A charge supplying apparatus in a frequency synthesizer includes first and second charge supply units. The first charge supply unit is activated for generating a first voltage coupled to a loop filter, and the second charge supply unit is activated for generating a second voltage coupled to the loop filter. A control unit has a mode determining unit that activates one of the first and second charge supply units from comparing a reference frequency with an output frequency. The mode determining unit also generates at least one control signal for adjusting the first voltage by binary increments for decreasing a difference between the reference and output frequencies.

Charge supply apparatus and method in frequency synthesizer

A dual frequency synthesizer includes a reference oscillator, an R counter, a first fractional-N phase-locked loop (for a receiving channel) and a second fractional-N phase-locked loop (for a transmitting channel) and one shared sigma-delta modulator. The reference oscillator outputs a reference oscillation frequency clock. The R counter outputs a reference frequency clock based on the reference oscillation frequency clock. The first fractional-N phase-locked loop (PLL) (for a receiving channel) generates a first (receiving channel frequency) clock based on the reference frequency clock. The second fractional-N phase-locked loop (for a transmitting channel) generates a second (transmitting channel frequency) clock based on the same reference frequency clock. Both fractional-N phase-locked loops share a common sigma-delta modulator. Therefore, the chip size of the dual frequency synthesizer may be reduced.

Frequency synthesizer and frequency synthesis method

A fractional-N frequency synthesizer supporting multi-band operation, having variable frequency resolution obtained by sigma-delta modulating a multi-bit frequency resolution control signal having at least one pulse, the at least one pulse having a period of P and a variable duty cycle. Frequency resolution can be increased by changing the duty cycle and without increasing input bits to the sigma-delta modulator. Thus, a core size of the sigma-delta modulator may be reduced.

Frequency synthesizer having variable frequency resolution, and fractional-N frequency synthesizing method using sigma-delta modulation of frequency control pulses

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Bucheon-si, South Korea

Hwa-yeal Yu