Samsung Electronics Co., Ltd.

Hwa-Sung Rhee

Ho Young Lee

Tetsuji Ueno

Seung-Hwan Lee

Dong-Suk Shin

Ho Joong Lee

Hyun-Jo Kim

Seung-hwan Lee

Ji-Hye Yi

Jae-Yoon Yoo

Yoon-Hae Kim

Ueno Tetsuji

Jae-yup Chung

Hee-Don Jeong

Nae-in Lee

Myung-Sun Kim

Moon-han Park

Chang-Wook Moon

Se-wan Park

Jong-shik Yoon

Ju-Youn Kim

Hyun-Suk Kim

Jong-Mil Youn

Keun-Hwi Cho

Hion-suck Baik

Bo-Cheol Jeong

Weiwei Chen

Jong-Ho Lee

Jung-hyun Lee

Suk-Pil Kim

Ho Won Lee

Joong S Jeon

Myung-sun Kim

Yoon-seok Lee

Hyun-deok Yang

Sang-Hyun Woo

Byung-seo Kim

Hyun-suk Kim

Hyung-Suk Jung

Byung-Sung Kim

Jae-Kwang Choi

Moon-Han Park

Sung-Gun Kang

Jong-bong Park

Ju-Hyun Kim

Je-min Yoo

Jung-Yun Won

Jeong-Hyo Lee

Se-Young Cho

Ji-Yong Ha

Dae-Lim Kang

Seong-Yul Park

Ji-Young Choi

Byou-ree Lim

Wei-Hua Hsu

Zhan Zhan

Kyu-man Cha

Min-Ho Kwon

Jun-Suk Choi

Yeon-Sik Park

Min-Seob Kim

DongSuk Shin

Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.

Semiconductor device

A method of detecting failure of a semiconductor device includes forming an active fin on an active region of a substrate, the active fin extending in a first direction, forming a gate structure on the active fin, the gate structure extending in a second direction intersecting the first direction, forming source/drain layers on respective portions of the active fins at opposite sides of the gate structure, forming a wiring to be electrically connected to the source/drain layers, and applying a voltage to measure a leakage current between the source/drain layers. Only one or two active fins may be formed on the active region. Only one or two gate structures may be formed on the active fin.

Method of detecting failure of a semiconductor device

A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.

Semiconductor devices and methods of manufacturing the same

An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalls of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalls of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.

Integrated circuit devices and methods of manufacturing the same

A semiconductor device includes a fin-type pattern including a first short side and a second short side opposed to each other, a first trench in contact with the first short side, a second trench in contact with the second short side, a first field insulating film in the first trench, the first field insulating film including a first portion and a second portion arranged sequentially from the first short side, and a height of the first portion being different from a height of the second portion, a second field insulating film in the second trench, and a first dummy gate on the first portion of the first field insulating film.

An integrated circuit (IC) device includes a fin-type active region formed in a substrate, a step insulation layer on at least one sidewall of the fin-type active region, and a first high-level isolation layer on the at least one sidewall of the fin-type active region. The fin-type active region protrudes from the substrate and extending in a first direction parallel to a main surface of the substrate, includes a channel region having a first conductivity type, and includes the stepped portion. The step insulation layer contacts the stepped portion of the fin-type active region. The step insulation layer is between the first high-level isolation layer and the at least one sidewall of the fin-type active region. The first high-level isolation layer extends in a second direction that is different from the first direction.

Integrated circuit device and method of manufacturing the same

Provided are method of fabricating semiconductor device and computing system for implementing the method. The method of fabricating a semiconductor device includes forming a target layer, forming a first mask on the target layer to expose a first region, subsequently forming a second mask on the target layer to expose a second region separated from the first region in a first direction, subsequently forming a third mask in the exposed first region to divide the first region into a first sub region and a second sub region separated from each other in a second direction intersecting the first direction, and etching the target layer using the first through third masks such that the first and second sub regions and the second region are defined in the target layer.

Method of fabricating semiconductor device and computing system for implementing the method

An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalk of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalk of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.

A test pattern of a semiconductor device is provided, which includes first and second fins formed to project from a substrate and arranged to be spaced apart from each other, first and second gate structures formed to cross the first and second fins, respectively, a first source region and a first drain region arranged on the first fin on one side and the other side of the first gate structure, a second source region and a second drain region arranged on the second fin on one side and the other side of the second gate structure, a first conductive pattern connected to the first and second drain regions to apply a first voltage to the first and second drain regions and a second conductive pattern connecting the first source region and the second gate structure to each other.

Test pattern of semiconductor device

A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer insulating layer covering the gate structure, a blocking pattern disposed on the first interlayer insulating layer, and a jumper pattern disposed on the blocking pattern. The jumper pattern includes jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate exposed at both sides of the gate structure, and a jumper section configured to electrically connect the jumper contact plugs.

Semiconductor device having jumper pattern and blocking pattern

A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate insulation layer formed on a silicon substrate, at least one nanorod embedded in the gate insulation layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate insulation layer between the source electrode and the drain electrode.

Field effect transistor having germanium nanorod and method of manufacturing the same

A semiconductor device includes an interlayer dielectric layer on a substrate, the interlayer dielectric layer having an upper surface, a lower plug extending down into the interlayer dielectric layer from the upper surface of the interlayer dielectric layer, the lower plug having an upper surface, a first dielectric layer pattern on the upper surface of the lower plug, at least a portion of the first dielectric layer pattern being directly connected to the upper surface of the lower plug, a first metal electrode pattern on the first dielectric layer pattern, a first upper plug electrically connected to the first metal electrode pattern, and a second upper plug on the lower plug, the second upper plug being spaced apart from the first upper plug.

Semiconductor device comprising capacitor and method of manufacturing the same

A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.

Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same

Growing community of inventors

Seongnam-si, South Korea

Hwa-Sung Rhee