Samsung Electronics Co., Ltd.

Hwa-seok Oh

Kyung-Phil Yoo

Young-Min Lee

Sung-Ho Seo

Seong-Yong Jang

Seok-Won Ahn

Sung-Ha Kim

Jin-Hyeok Choi

Jung-Pil Lee

Soon-Bok Jang

Young-wook Kim

Jae-Phil Kong

Jong-Uk Song

Hyun-Tae Park

Myung-Sub Shin

Hyun-Ju Yi

A method of operating a storage device includes receiving, from a host, a first packet containing a buffer address indicating a location of a data buffer selected from among a plurality of data buffers in the host, parsing the buffer address from the first packet, and transmitting a second packet containing the buffer address to the host in response to the first packet.

Storage device for interfacing with host and method of operating the host and the storage device

Provided are a storage device, a storage system, and a method of operating the same. A storage device communicably connected to a host may include a non-volatile memory configured to store at least one piece of boot data necessary for booting the storage device; and a device controller configured to receive an interface initialize command (IFIC) from the host, predict requested boot data requested by the host from among the at least one piece of boot data based on the IFIC, and control the non-volatile memory to read the requested boot data.

Storage device, storage system and method of operating the same

An operating method of a semiconductor device and a memory system, each including a multi-connection port, includes: receiving connection information of a first device while connecting to the first device; updating information of a management table by using the connection information; and generating and transmitting a first packet including the connection information of the first device to a second device pre-connected to the memory system.

Operating methods of semiconductor device and memory system each including multi-connection port, and communication method of storage system

A non-volatile memory system includes a memory controller, where the memory controller includes a first region including a first memory that stores compressed code, and a second region including a second memory that stores decompressed code. Power supplied to the first region and the second region is controlled according to an operation mode of the non-volatile memory system.

Non-volatile memory system, memory card having the same, and operating method of non-volatile memory system

A memory swapping method and a data processing system using the same, the memory swapping method including receiving queue information for a memory swapping task from a host device; performing part of the memory swapping task in a storage device based on the queue information; receiving a command corresponding to the queue information from the host device after performing of the part of the memory swapping task is completed; and performing a remaining part of the memory swapping task according to the command by using a result of the part of the memory swapping task that had been previously performed.

Memory swapping method, and host device, storage device, and data processing system using the same

A storage device includes a nonvolatile memory and a connector configured to connect the storage device to a host. The connector includes a detection terminal that provides a detection voltage to the host, a sensing resistor electrically connected to the detection terminal and having a resistance value that determines the level of the detection voltage, and a power supply terminal that receives a power supply voltage from the host, wherein the power supply voltage is selected by the host in response to the detection voltage.

Storage system, host, storage device, and methods of operating same

A non-volatile memory and a method of controlling an erase operation of the non-volatile memory using a controller are provided. The method of controlling the erase operation includes beginning performance of the erase operation, monitoring a next command to be performed in the non-volatile memory while performing the erase operation, determining an erase status, and continuing, suspending or canceling the erase operation based on the determination result of the erase status.

Method of controlling erase operation of a memory and memory system implementing the same

A duty ratio correction circuit for correcting a duty ratio of a clock signal. The duty ratio correction circuit includes an asymmetry buffer that receives a clock signal and adjusts a duty ratio of the clock signal in response to control signals; a clock generating circuit that is connected to the asymmetry buffer and detects the duty ratio of the clock signal; and a controller that generates the control signals according to the duty ratio of the clock signal. An operation of the controller is recorded as a program on a computer-readable recording medium.

Duty ratio correction circuit

A method of generating interrupts and a network interface card, which minimizes the number of times that interrupts are generated, are provided. The method includes receiving data frames; estimating a first and second time delay and counting a number of received data frames; determining whether the first time delay has passed and generating an interrupt if the time reaches the first delay time, counting the number of data frames if the first time delay has not passed and generating the interrupt if the number of data frames is equal to N; determining whether the second time delay has passed if the number of data frames is not equal to N and generating the interrupt if the second time delay has passed; stopping operations of estimating the first and second time delays and counting the number of data frames in response to the interrupt generated, and transmitting the received data frames.

Growing community of inventors

Yongin-si, South Korea

Hwa-seok Oh