Intel Corporation

Hwa Chaw Law

Yu Ying Ong

Kiun Kiet Jong

A modular Error Correction Code (ECC) scheme in a multi-channel IO link of an integrated circuit device is provided. The integrated circuit device may include core logic circuitry that may be configured after manufacturing. To accommodate the resulting variation, the modular ECC scheme may allow for partitioning a parity check matrix associated with the configuration of the core logic and peripheries coupled to the core logic. The parity check matrix is partitioned into smaller block matrices that is programmable. Multiple ECC modules corresponding to the block matrices are used to provide error detection and correction in the multi-channel IO link. The modular ECC scheme combined with programmable matrices (configurability) enables multi-channel IO link to be flexible to form different IO topologies.

Modular error correction code circuitry

An inter-die double data rate (DDR) data transfer scheme is provided. In particular, the data transfer scheme utilizes an error correction code (ECC) encoding scheme that exploits the DDR property that a single microbump defect can only yield four possible error scenarios. A specialized single error correcting, double error detecting, and double adjacent error correcting (SEC-DED-DAEC) encoding scheme that imposes at least four parity check matrix constraints may be used. Configured and operated in this way, a fewer number of parity check bits are required to detect data bit errors associated with a single defective microbump.

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Kuala Langat, Malaysia

Hwa Chaw Law