Micron Technology Incorporated

Huy Thanh Vo

Charles L Ingalls

Mark R Thomann

Suryanarayana B Tatapudi

Adam Saleh El-Mansouri

Yantao Ma

William K Waller

Ferdinando Bedeschi

Kang-Yong Kim

Jacob Robert Anderson

Glen Earl Hush

Todd A Merritt

Umberto Di Vincenzo

Riccardo Muzzetto

Hua Zheng

Joseph C Sher

Hyun Yoo Lee

Victor Wong

David D Siek

Nicholas Van Heel

Timothy Mowry Hollis

Scott James Derner

John David Porter

Jeffrey P Wright

Donald M Morgan

Greg A Blodgett

Christopher John Kawamura

Patrick J Mullarkey

Michael Amiel Shore

Tae Hyoung Kim

Layne G Bunker

Dirgha Khatri

Hyunyoo Lee

Zer Liang

Tadashi Yamamoto

Howard Kirsch

Christopher K Morzano

Loren L McLaury

Raymond A Turi

Luoqi Li

Mark Thomman

An apparatus may include a sense amplifier with a single column select transistor, a local input/output line selectively couplable to a first bit line through the column select transistor, and a read/write gap comprising at least a first transistor and a second transistor. The first transistor may be couplable to a read select signal and a complimentary local input/output line and the second transistor is couplable to the complimentary local input/output line and a global input/output line.

Single column select architecture for sense amplifier circuity

A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

Pre-sense gut node amplification in sense amplifier

Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.

Source follower-based sensing scheme

Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

Sensing a memory cell

Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.

Arbitrated sense amplifier

Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.

Multi-stage memory sensing

Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, a second adjustable delay line included in the internal data strobe signal pathway, and a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.

Apparatuses and methods for providing constant DQS-DQ delay in a memory device

Systems and methods are provided for implementing an array reset mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.

Systems and methods for memory cell array initialization

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Boise, ID, United States of America

Huy Thanh Vo