Rambus Inc.

Apple Inc.

Google Inc.

Freescale Semiconductor,inc.

Palm, Incorporated

Nxp Usa, Inc.

Palmone, Incorporated

Qualcomm Incorporated

Hewlett-packard Development Company, L.p.

Nvidia Corporation

Wavelink Corporation

Huy M Nguyen

Benedict C Lau

Vijay Gadde

Roxanne T Vu

Leung Yu

Jade M Kizer

Andrew Timothy Szybalski

Stephen Chau

Andrea Lynn Frome

Derek King Prothro

Jerry Howard Morrison

Stephane Lafon

Seong Hoon Lee

Lawrence K Lam

James A Gasbarro

Kambiz Kaviani

Brian S Leibowitz

Amir Amirkhany

Kyung Suk Oh

Yohan Usthavia Frans

John M Wilson

Lei Luo

Bret G Stott

Steven J Shiozaki

Chaofeng Huang

Sivakumar Doraiswamy

Michael D Bucher

Alan Joseph Carlin

Mitesh D Katakwar

Eugene C Ho

Adam Chuen-Huei Chou

Hugo M Cavalcanti

Hsuan-Jung (Bruce) Su

Woopoung Kim

Jared L Zerbe

Jaeha Kim

Troy Hulick

Reza Navid

Hamed Ghassemi

Kenneth A Jenks

Huabo Chen

Xudong Shi

Yu Chang

Jason Chia-Jen Wei

William C Moyer

Scott C Best

Ravindraraj Ramaraju

Thomas J Giovannini

Shayan Zhang

Andrew Christopher Russell

Gary L Miller

David R Bearden

William D Webb, Ii

Firas Najeh Abughazaleh

Troy L Cooper

James Andrew Welker

Todd W Bystrom

William D Webb

Ke Dong

Maciej Bajkowski

Benedict Chung-Kwong Lau

Cristian Gozzi

Chuen-Huei Chou

Jeffrey Freeman

Dennis Hwang

Kansinee Adsanatham

Brian Tran

Vinay Kumar Kothiyal

Wayne Takata

Christos Kotsiopoulos

Xinfa Wu

Sean Howarth

Jonathan W McCallum

Tola Chin

Venkatarama Mohanareddy Mooraka

Dennis Huanyu Wu

Zhenye Zhu

Xuchen Zhang

Sivakumar Doriaswamy

Chris Kotsiopoulos

Circuits for reflection cancellation in single-ended signaling are disclosed. A transmission circuit includes a control circuit configured to receive a plurality of input signals that include a plurality of symbols having at least one bit and a data driver circuit configured to generate a particular signal on a transmission medium using a particular symbol of the plurality of symbols. The transmission circuit further includes a reflection cancellation circuit configured to, after a generation of the particular signal, generate a reflection cancellation signal on the transmission medium using an inverted value of a different symbol of the plurality of symbols received prior to the particular symbol. A first composite of the particular signal and the cancellation signal is readable at a load as a value of the particular symbol, wherein the load is configured to receive a transmitted signal via the transmission medium.

Reflection cancellation for single-ended signaling

Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

Integrated circuit with configurable on-die termination

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Calibration methods and circuits to calibrate drive current and termination impedance

An apparatus includes first and second receiver circuits and a decision circuit. The first receiver circuit is configured to generate a first data symbol from a particular input data symbol of a plurality of input data symbols included in an input signal. The second receiver circuit is configured to generate a second data symbol from the particular input data symbol. The decision circuit is configured to select, using respective values of one or more previous output data symbols, either the first or second data symbol as a current output data symbol. In response to a change in value between successive input data symbols, the first and second receiver circuits are configured to generate the first and second data symbols with respective data valid windows with different durations.

Serial data receiver with decision feedback equalization

A phase to digital converter (PDC) generates a digital output that represents a phase difference between first and second clocks. The PDC includes a gated ring oscillator (GRO), which includes N signal delay elements coupled together in a ring via a logic gate, wherein a 1st signal delay element of the ring comprises an input coupled to an output of the logic gate, and wherein a Nth signal delay element of the ring comprises an output coupled to a first input of the logic gate. A convertor is coupled to the GRO and configured to generate low order bits of the digital output based on outputs of the logic gate and the N signal delay elements. A first counter includes an input coupled to an output of one of the N signal delay elements or the logic gate, wherein the first counter is configured to generate a first digital counter value. A second counter includes an input coupled to an output of another one of the N signal delay elements or the logic gate, wherein the second counter is configured to generate a second digital counter value. The PDC generates the digital output signal based on the low order bits and one of the first and second digital counter values.

Phase to digital converter

A transceiver circuit having a T-coil circuit, inductive termination, and an equalization circuit is disclosed. The transceiver includes a transmitter having an output coupled to a first node, and a receiver having an input coupled to the first node. A T-coil circuit is coupled between the first node and an input/output (I/O) node. The T-coil circuit includes first and second inductors coupled in series between the first node and the I/O node, the inductors being coupled at a second node. A termination circuit is coupled between the first node and a reference node, the termination circuit including a third inductor. The transceiver circuit also includes an equalization circuit configured to convey an equalization signal to the second node.

Transceiver circuit having T-coil, inductive termination, and equalization

A method and apparatus for receiving reduced voltage swing signals is disclosed. A first amplifier may generate a first intermediate signal based on a difference between voltage levels of a first and second input signals, and a second amplifier may generate a second intermediate signal based on a difference in the voltage levels between the second and first input signals. A regenerative amplifier may increase a difference in the voltage level of the first and second intermediate signals using regenerative feedback and the voltage levels of the first and second input signals. A latch circuit may generate first and second output signals using the first and second intermediate signals.

Wide range input voltage differential receiver

A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to the first connectivity circuitry by the first processor bus and configured to provide first bus transactions, to be provided to the second connectivity circuitry, to the first processor bus, the first connectivity circuitry configured to utilize a multiple simultaneous outstanding transaction capability supporting multiple simultaneous outstanding write transactions concurrent with multiple simultaneous outstanding read transactions, the second connectivity circuitry configured to provide processor bus flow control information and elasticity buffer status information pertaining to the elasticity buffer to the first connectivity circuitry via a common message for flow control.

Inter-processor communication method for access latency between system-in-package (SIP) dies

A method includes receiving user data packets from customer premises equipment (CPE) in communication with a network terminal over a communication link and enabling a network terminal-side loopback mode to establish a closed traffic test loop across the communication link between the network terminal and the CPE. The received user data packets indicate that a CPE-side loopback mode is enabled. The method also includes injecting a number of data bits into the closed traffic test loop until a saturation threshold of the communication link is satisfied, and when the number of data bits injected into the closed traffic test loop satisfies the saturation threshold, determining a packet error-rate of the number of data bits circulating in the closed traffic test loop. After determining the packet error-rate, the method also includes removing the closed traffic test loop across the communication link between the network terminal and the CPE.

Line rate ethernet traffic testing

Systems, apparatuses, and methods for generating a reference voltage are described. In various embodiments, an interface between a memory and a processor uses a reference voltage generator to generate a reference voltage for a single pin or a small group of pins. The generator generates a default reference voltage from a first tap in a resistor ladder, injects current with a current controller into a second tap of the resistor ladder when the generator receives an indication to generate a larger reference voltage, and draws current from a third tap of the resistor ladder when the generator receives an indication to generate a smaller reference voltage. The generator also generates a high threshold voltage independent of a low threshold voltage after calibration.

Per-pin compact reference voltage generator

Growing community of inventors

San Jose, CA, United States of America

Huy M Nguyen