Northern Telecom Limited

Canadian Patents and Development Limited/societe Canadienne Des Brevets

Hussein M Naguib

Iain D Calder

Abdalla A Naem

David R Baraff

Vu Q Ho

Steven Kos

Cornelis Blaauw

Albert R Boothroyd

Ahmad Aftab

Syed M Ahmed

In a metal oxide semiconductor field effect transistor fabrication process, refractory metal is deposited over designated source and drain areas within a silicon substrate. Refractory metal and silicon at the interface is then mixed by ion implantation of a heavy neutral ion species such as germanium. To minimize source/drain junction depth, the source and drain locations can be subjected to bombardment by a lighter ion such as silicon which amorphizes silicon to a predetermined depth under the designated source and drain regions and so substantially confines dopant diffusion to the silicon amorphized region. To render the source and drain of desired conductivity type, an ion implantation of a non-neutral ion is then performed.

Process of fabricating MOS devices having shallow source and drain

An integrated circuit is fabricated with some redundant capacity by forming potential electrically conducting links which can subsequently be made electrically when extra circuit capacity is required. Field oxide is grown on a silicon substrate and then a layer of polysilicon deposited over the oxide. At the redundancy sites where electrical connections may subsequently be made, an anti-reflective silicon nitride coating is deposited and photodefined. The areas of this coating are used as masks in order to diffuse dopant into the polysilicon at parts of the polysilicon laterally adjacent the redundancy sites. When later it is necessary to bring spare capacity into the circuit the complete circuit is scanned with a continuous wave laser. The laser melts the polysilicon under the nitride mask permitting the dopant to diffuse from the adjacent parts of the polysilicon and so form a conducting link. However under parts of the polysilicon not covered by an anti-reflective coating the polysilicon is not melted by the laser beam and so its conductivity remains unchanged. The fabrication process is self-aligned since the intrinsic or undoped region of the polysilicon is the same as the region which is melted. The method for making the electrical links does not require precise positioning and focussing of the laser beam as in known methods.

Laser activated polysilicon connections for redundancy

Semiconductive photoanodes formed of titanium dioxide (TiO.sub.2) are known for use in photoelectrochemical cells. They have been made by various techniques, including chemical vapor deposition, thermal oxidation or anodic oxidation of thin titanium foils, hot pressing of TiO.sub.2 powder, and plasma spraying. The present invention provides a method for the fabrication of TiO.sub.2 thick film photoanodes, which method is simple, inexpensive and suitable for mass production of large area plates. The method comprises screen printing a film of conductive material on a clean alumina substrate which is then heated to fuse the conductive material into a conductive layer. A first layer of TiO.sub.2 particles in an organic carrier is then screen-printed over the conductive layer, at least 10% of the TiO.sub.2 being of anatase form. The structure is then heated to burn off the organic carrier and to transform at least part of the TiO.sub.2 from anatase form to rutile form, this resulting in good adhesion of the TiO.sub.2 layer to the conductive layer. A second layer of TiO.sub.2 is then screen-printed over the first layer and heated, the second layer being provided in case there should be pinholes in the first layer which would adversely affect the anode structure when submersed in an electrolyte. The resulting structure is then heated in a reducing atmosphere, e.g. anhydrous ammonia or hydrogen, to transform the TiO.sub.2 to TiO.sub.2-x where x is between 0 and 1, to reduce the electrical resistivity of the films.

Method of preparing TiO.sub.2 thick film photoanodes for

In a stacked metal-oxide-semiconductor (SMOS) transistor, the transistor source, drain and channel each have a lower part formed in a silicon substrate and an upper part composed of recrystallized polysilicon. The device gate is located between the upper and lower channel parts. By vertically integrating a MOS transistor, performance limitations imposed by the direct scaling approach to device miniaturization are avoided.

Stacked MOS transistor

In the manufacture of VLSI (very large scale integrated) MOS (metal-oxide-semiconductor) circuits, a polysilicon gate is deposited on an oxide layer overlaying a silicon substrate. Ideally, the polysilicon gate is made extremely small and with sharply defined vertical boundaries. The invention proposes depositing a polysilicon layer, covering a region of the layer with an antireflective coating, and laser annealing the layer. Laser radiation is absorbed to a higher level by the coated region than elsewhere and consequently the polysilicon layer in this region melts and recrystallizes into large grains. The polysilicon layer is then etched using etch conditions ensuring preferential etching of unrecrystallized polysilicon in comparison with recrystallized polysilicon. Consequently, except at the coated region, the polysilicon is etched quickly and there is very little undercutting of the gate region. Preferential etching methods based on differing dopant levels in polysilicon are known but do not produce the sharp edge definition enabled using the present process.

Method of fabricating semiconductor devices using laser annealing

Each thick film resistive print element of a thermal print bar operated in a scan mode is series connected to a thick film switch which sets a voltage threshold to isolate the element from periodic scan pulses unless coincident with an element selecting data pulse in which case the thick film undergoes joule heating which causes it to switch and its series-connected resistive element undegoes joule heating.

Growing community of inventors

Kanata, Canada

Hussein M Naguib