Intel Corporation

Hussein Alameer

Kjersten E Criss

Uksong Kang

Kuljit Singh Bains

John B Halbert

Rajat Agarwal

Wei Wu

Vivek Joy Kozhikkottu

Jongwon Lee

An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.

Memory device with local cache array

An embodiment of a semiconductor apparatus may include technology to provide two or more dynamic random access memory devices, and provide access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel. Other embodiments are disclosed and claimed.

Pseudo-channeled DRAM

A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.

Stacked memory chip device with enhanced data protection capability

Growing community of inventors

Portland, OR, United States of America

Hussein Alameer