King Fahd University of Petroleum and Minerals

King Abdulaziz City for Science and Technology

Saudi Arabian Oil Company

Hussain Alzaher

Abdulrahman Alshuhail

Alaa El-Din Hussein

Abdullatif Al-Shuhail

Mohammad Khalaf Alghamdi

Yaqub Al-Hussain Mahnashi

Noman Ali Tasadduq

Emad Abdo Mohammed Al-Hemyari

A second-order low-pass canonical filter designed for precise signal processing and a method for assembling and a method for low pass filtering a current signal are described. The filter comprises two main stages. The first stage includes a current source that feeds into a first programmable current division network (CDN), which is in series with a first current follower (CF) having a single output terminal. This arrangement is followed by a first three output terminal CF circuit. The second stage consists of a second CDN network connected in series with the negative output of the first three output terminal CF circuit. A second single output terminal CF in series with the second CDNis connected to a second three output terminal CF, whose negative output terminal provides a low pass filtered output current I. This filter architecture is particularly advantageous for applications requiring stable and adjustable frequency filtering capabilities.

Canonical lowpass filter with digitally programmable cutoff frequency settings using current followers

A system for a first digitally controlled grounded inductor simulation circuit may include an OP-AMP, a digitally controlled current amplifier (DCCA), a voltage buffer, two resistors, and a capacitor. The first digitally controlled grounded inductor simulation circuit allows adjustment of an equivalent inductance value (CRR/A) through programming a digitally controlled current gain (A) of the DCCA. A system for a second digitally controlled grounded inductor simulation circuit includes an OP-AMP, a digitally controlled current amplifier (DCCA), a dual output current follower (CF), an active current division network (CDN), two resistors, and a capacitor. The second digitally controlled grounded inductor simulation circuit allows adjustment of an equivalent inductance value (CRR/αA) via programming the active CDN and the DCCA.

Digitally controlled ground inductor simulation circuits

A digitally controlled grounded capacitor multiplier includes: a single capacitor directly connected at one end to an input voltage and at another end to a negative input of an operational amplifier; the operational amplifier including a negative feedback loop; and a digitally controlled current amplifier (DCCA) connected to an output of the operational amplifier. The DCCA digitally controls the digitally controlled grounded capacitor multiplier. The digitally controlled grounded capacitor multiplier comprises only two active devices consisting of the operational amplifier and the DCCA.

Digitally controlled ground capacitor multiplier

A current-mode Schmitt Trigger includes a plurality of current output stages connected to a common supply voltage that powers the current-mode Schmitt Trigger, a main input on one of the current output stages that receives an input current, and a non-inverting output on a different one of the current output stages that is shorted to the main input to establish a positive closed-loop feedback and supplies a non-inverting output current as the input current. The current-mode Schmitt Trigger includes only active components.

Current-mode Schmitt trigger using current output stages

A square wave oscillator includes a Schmitt Trigger with a first output that outputs a first output current, a capacitor connected to the first output of the Schmitt Trigger, and a resistor that connects the capacitor to an input of the Schmitt Trigger to form a closed-loop negative feedback. The closed-loop negative feedback sustains an oscillation of the square wave oscillator and causes a frequency and an amplitude of the oscillation to be independent of a supply voltage of the Schmitt Trigger.

Current-mode square wave oscillator

A digitally controlled grounded capacitance multiplier circuit system and method is disclosed. The capacitance multiplier (CM) circuit comprises an op-amp, a digitally controlled current amplifier and two resistors in addition to a reference capacitor. The CM circuit is designed using complementary metal-oxide-semiconductor (CMOS) technology. The value of the equivalent capacitance can be adjusted through digitally programming the gain of the current amplifier. The CM circuit provides a significant multiplication factor while using two active devices.

Digitally controlled grounded capacitance multiplier

A multiple-gain transconductance amplifier circuit is presented. It is developed by utilizing programmable gain source-coupling differential pair output stage forming multiple-gain transconductance amplifier outputs. A reconfigurable n-order filter based on a multi-gain transconductance amplifier where the multi-gain transconductance amplifier includes a linear voltage-to-current converter and a programmable current-folding output stage was implemented. The filter achieves independent programmability while still using a single active device per pole. Further, the proposed multiple-gain transconductance amplifier can be employed to design poly phase filters and transconductance amplifier cell for an amplifier-based low-dropout regulator.

Multi-gain transconductance amplifier

A CMOS channel select filter for DVB-H direct-conversion receives based on a transresistance amplifier (TRA) is disclosed. The channel select filter includes a fully differential transresistance amplifier (FDTRA) configured to change an input current at each differential input terminal to a voltage at each differential output terminal based on an impedance at a corresponding differential impedance terminal. The channel select filter also includes two feedback resistors, each having one end connected to a respective differential output terminal of the FDTRA and having another end connected to the node, two first capacitors, each connected between ground and the node, and two second capacitors, each connected between ground and a respective differential impedance terminal.

Channel select filter having a fully differential transresistance amplifier and CMOS current amplifier

Low-power channel select filter using transresistance amplifier for DVB-H receivers

A reconfigurable integrator/differentiator circuit includes: a first input terminal; a first output terminal; a first current follower having a second input terminal, a second inverting output terminal providing feedback to the first input terminal, a third non-inverting output terminal being connected to the first output terminal, and a fourth inverting output terminal; a second current follower having a third input terminal, a fifth inverting output terminal providing feedback to the first output terminal, and a sixth non-inverting output terminal being connected to the first input terminal; a single capacitor being connected between the fourth inverting output terminal and ground; a first resistor being connected between the first input terminal and the second input terminal; and a second resistor being connected between the fourth inverting output terminal and the third input terminal.

Reconfigurable integrator/differentiator circuit using current follower based simulated inductor

Active-RC low-pass filters based on R-0.5R ladders are implemented to provide high linear and low power design solutions for integrated biomedical applications. Among various R-&#x3b1;R ladders family, R-0.5R ladders provide the best low frequency selectivity characteristics. The filters exhibit ultra-low pole frequencies and occupy relatively compact silicon areas by using the R-0.5R ladders.

Ultra-low frequency bio-medical active-RC lowpass filters

A reconfigurable integrator/Differentiator circuit includes: a first input terminal; a first output terminal; a first current follower amplifier having a second input terminal, a second inverting output terminal, and a third non-inverting output terminal, wherein the second inverting output terminal provides feed back to the first input terminal and the third non-inverting output terminal is directly connected to the first output terminal; a second current follower amplifier having a third input terminal, a fourth inverting output terminal, and a fifth non-inverting output terminal, wherein the fourth inverting output terminal provides feed back to the first input terminal and the fifth non-inverting output terminal is directly connected to the first output terminal; a single resistor being connected between the first input terminal and the second input terminal, and a single capacitor being connected between the first input terminal and the third input terminal.

Reconfigurable intergrator/differentiator circuit based on current follower

The reconfigurable Nth-order filter includes a CCII adopting active current division networks for implementing the proposed filter. This digitally programmable second generation current conveyor leads to wide control of filter coefficients for reconfiguration of the filter. Programmability characteristics are demonstrated through experimental results obtained from integrated circuit chips fabricated in a 0.18 &#x3bc;m CMOS process.

Reconfigurable Nth-order filter

The optimal low power complex filter, as a second order complex filter, is based on current amplifiers (CAs) and is utilized to implement a 4th order current-mode filter that can be used for intermediate frequency (IF) applications, such as, for example, low-IF Bluetooth receivers. Fabricated in a standard 0.18 &#x3bc;m CMOS technology, experimental results show that the present design offers improved characteristics over the existing solutions in terms of power consumption and spurious-free dynamic range (SFDR). The 4order filter exhibits in-band SFDR of 65.8 dB while consuming only 1 mW.

Optimal low power complex filter

The fully integrated DC offset compensation servo feedback loop is an integrator that measures the output signal DC component, and then feeds back and subtracts the measured DC component from the input signal. A larger integrator time constant lowers the high pass corner frequency, which must be very small in order to minimize the loss of the low frequency component of the desired signals. The large time constant is achieved on an integrated circuit by the use of a class-AB fully differential opamp in conjunction with an R-2R ladder as a circuit element to accomplish an integrated large time constant integrator. The R-2R ladder is configured as a digitally programmable resistor.

Growing community of inventors

Dhahran, Saudi Arabia

Hussain Alzaher