Texas Instruments Corporation

Sematech, Inc.

Husam N Alshareef

Malcolm John Bevan

Hiroaki Niimi

Haowen Bu

Rajesh B Khamankar

Michael Francis Pas

Manfred Ramin

April Gurba

Mark H Somervell

Brian Keith Kirkpatrick

Ajith Varghese

Clinton L Montgomery

Luigi Colombo

Prashant Majhi

Mark R Visokay

Kisik Choi

Antonio Luis Pacheco Rotondaro

Weize W Xiong

Anand T Krishnan

Toan Tran

Cathy A Chancellor

Manuel Quevedo Lopez

Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

System and method for mitigating oxide growth in a gate dielectric

Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.

Work function adjustment with the implant of lanthanides

A method for manufacturing a semiconductor device includes forming a gate electrode over a gate dielectric. The gate dielectric is formed by forming a lanthanide metal layer over a nitrided silicon oxide layer, and then performing an anneal to inter-diffuse atoms to form a lanthanide silicon oxynitride layer. A gate electrode layer may be deposited before or after the anneal. In an embodiment, the gate electrode layer includes a non-lanthanide metal layer, a barrier layer formed over the non-lanthanide metal layer, and a polysilicon layer formed over the barrier layer. Hafnium atoms may optionally be implanted into the nitrided silicon oxide layer.

Method of forming a high-k gate dielectric layer

Metal Oxide Semiconductor (MOS) transistors fabricated using current art may utilize a nitridation process on the gate dielectric to improve transistor reliability. Nitridation by the current art, which involves exposing the gate dielectric to a nitridation source, produces a significant concentration of nitrogen at the interface of the gate dielectric and the transistor substrate, which adversely affects transistor performance. This invention comprises the process of depositing a sacrificial layer on the gate dielectric prior to nitridation, exposing the sacrificial layer to a nitridation source, during which time nitrogen atoms diffuse through the sacrificial layer into the gate dielectric, then removing the sacrificial layer without degrading the gate dielectric. Work associated with this invention on high-k gate dielectrics has demonstrated a 20 percent reduction in nitrogen concentration at the gate dielectric&#x2014;transistor substrate interface.

Nitrogen profile in high-K dielectrics using ultrathin disposable capping layers

Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.

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Murphy, TX, United States of America

Husam N Alshareef