International Business Machines Corporation

Huo Ding Li

Rong Yan

Yu Fen Yuan

Sheng Xu

Kuan Feng

Xing Liu

Liang Chen

Xing S H Liu

Wei Liu

Qi Chen

Jun He

Guang Lei Li

An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords that the processor organizes into functionally common subsets. The processor includes a general purpose processor (GPU) and one or more special purpose processor (SPUs). An SPU of the processor may includes two SPU buffers. The processor first transfers bitstream data into GPU buffer memory and then populates the SPU buffers one after another with bitstream data. The SPU buffers may each include an overlap region that the SPU populates with the same bitstream data. The SPU parses the bitstream data in the SPU buffers in alternating fashion. The SPU may shift parsing from the one SPU buffer to the other SPU buffer when parsing reaches a subset boundary within an overlap region.

Variable-length code (VLC) bitstream parsing in a multi-core processor with buffer overlap regions

Specified data is distributed in a High-Performance Computing cluster comprising a Management node and M computation nodes where M is an integer greater than one, by the method comprising: dividing the M computation nodes into m layers where m is an integer greater than one; dividing the specified data into k shares where k is an integer greater than one; distributing, by the Management node, the k shares of data to a first layer of computation nodes as sub-nodes thereof, each node of the first layer obtaining at least one share of data therein; distributing, by each of the computation nodes, the share(s) of data distributed by a parent node thereof to sub-nodes thereof; and requesting, by each of the computation nodes, the remaining specified data to other computation nodes, to thereby obtain all the specified data.

Method and system for data distribution in high performance computing cluster

An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords for interpretation. The processor includes a general purpose unit (GPU) and a special purpose unit (SPU). The GPU includes GPU buffers and the SPU includes SPU buffers. After populating one GPU buffer with bitstream data, the processor populates another GPU buffer with subsequent bitstream data. The processor may populate the GPU buffers in alternating fashion. The processor populates one SPU buffer with bitstream data while parsing bitstream data in the other SPU buffer. The GPU of the processor populates the SPU buffers in alternating fashion. The size of the GPU buffers may be a multiple of the size of the SPU buffers. After the SPU buffers consume the bitstream data from one GPU buffer, the other GPU buffer transfers its bitstream data to the SPU buffers for parsing.

Asymmetric double buffering of bitstream data in a multi-core processor

An information handling system (IHS) may include a processor with multiple compute elements that decode pictures from an encoded video bitstream. Each compute element may perform a different part or sequential stage of a picture decoding process to obtain decoded pictures. A memory includes a decoded picture buffer that associates with a first stage of the sequential stages. The memory may also include respective decoded picture buffer snapshots for sequential stages other than the first sequential stage. A last sequential stage provides fully decoded pictures to a decoded picture pool in memory. The decoded picture buffer and decoded picture buffer snapshots may store pointers to decoded pictures in the decoded picture pool that the sequential stages need to perform decoding of pictures. In this manner, the sequential stages may share decoded pictures that the decoded picture pool stores.

Picture processing via a shared decoded picture pool

An information handling system includes a processor that may perform preprocessing on a variable-length code (VLC) bitstream before decoding the bitstream. The bitstream includes multiple codewords. The processor analyzes incoming VLC bitstream information and generates codeword table information for storage in a system memory or a VLC codeword tables location. The processor generates a VLC lookup table from the information in the VLC codeword tables and stores that VLC lookup table in a system memory of the IHS. The VLC lookup table may exhibit two dimensional indexing by leading zero count and bit-length possibility.

Preprocessing variable-length code (VLC) bitstream information

An information handling system includes a processor that may perform decoding of a variable-length code (VLC) bitstream after preprocessing the bitstream. The bitstream includes multiple VLC symbols as binary codewords. The processor analyzes incoming VLC bitstream information and generates VLC codeword symbol information in conformance with a VLC lookup table. The processor may access a 2 dimensional VLC lookup table in real time or on-the-fly. The VLC lookup table may reside in a system memory of the IHS. The single VLC lookup table may exhibit two dimensional indexing by leading zero count and bit-length possibility.

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Huo Ding Li