Motorola Corporation

International Business Machines Corporation

Other

Apple Inc.

Hunter Ledbetter Scales, Iii

Brett Olsson

Pradeep Kumar Dubey

Ronald Ray Hochsprung

Keith E Diefendorff

William C Moyer

William D Wilson

Charles P Roth

Keith Everett Diefendorf

Michael D Snyder

Cathy May

George P Hoekstra

Edward John Silha

Bradley Gene Burgess

Donald C Anderson

Mitchell K Alsup

Michael C Shebanow

Bradford Byron Beavers

A crossbar is implemented within multimedia facilities of a processor to perform vector permute operations, in which the bytes of a source operand are reordered in the target output. The crossbar is then reused for other instructions requiring multiplexing or shifting operations, particularly those in which the size of additional multiplexers or the size and delay of a barrel shifter is significant. A wide shift operation, for example, may be performed with one cycle latency by the crossbar and one additional layer of multiplexers or a small barrel shifter. The crossbar facility thus gets reused with improved performance of the instructions now sharing the crossbar and a reduction in the total area required by a multimedia facility within a processor.

Wide shifting in the vector permute unit

The data processing system loads three input operands, including two input vectors and a control vector, into vector registers and performs a permutation of the two input vectors as specified by the control vector, and further stores the result of the operation as the output operand in an output register. The control vector consists of sixteen indices, each uniquely identifying a single byte of input data in either of the input registers, and can be specified in the operational code or be the result of a computation previously performed within the vector registers. The control vector is specified by calculating the offset of a selected vector element of the input vector relative to a base address of the input vector and loading each element with an index equal to the relative offset. Alternatively, the generation of the alignment vector is made by performing a look-up within a look-up table. For additional loads from the same vector, the control vector does not change, since the alignment shift amount of the vector from an address boundary does not change. A permutation instruction can then be executed to load and shift the data to realign it in the output register at the vector boundary.

Method and apparatus for generating an alignment control vector

The invention relates to a method of using a &ldquo;bounds&rdquo; comparator scheme and to a &ldquo;bounds&rdquo; comparator circuit. The method of using this scheme or comparator circuit allows a quick and easy test to characterize, utilizing a single floating-point bounds comparison function, the location of a point with respect to pre-defined end- points. The single floating-point bounds comparison function represents an additional instruction to be incorporated within computer instruction set architectures when performing trivial acceptance testing during the generation of three-dimensional images or graphics.

Method and system for bounds comparator

A method and system is disclosed which summarizes the results of a classical single-instruction multiple-data SIMD predicate comparison operation, signaling whether all comparisons resulted in a false result or true result, and placing that status into a separate status register, such as the Power PC Condition Register. The method and system utilizes first and second status bits to support the signaling whether all element comparisons resulted in true or false. The first status bit is set when all element comparisons resulted in false (i.e. a NOR of all predicate comparison results), and the second status bit is set when all element comparisons resulted in true (i.e. an AND of all predicate comparison results). This capability allows control flow using conditional branching on the event when all comparison results are false or when all comparison results are true. The method and system of the present invention is useful in 3-D graphics such as lighting and trivial acceptance testing where executing down both paths of a branch and then selecting the correct result is not tolerable.

Method and system for a result code for a single-instruction multiple-data predicate compare operation

A data processing system includes a data processor (,) coupled to a memory system having a first memory, such as an L1 data cache (,), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (,) prefetches data elements of a vector into the first memory prior to processing such data elements. If a requested data element is not present in the first memory, a load request is issued to the second memory and to lower levels of the memory hierarchy until the requested data element is finally retrieved and stored in the first memory. The data processor (,) continues to prefetch subsequent data elements of the vector by considering the length of the data element and the stride of the vector. In one embodiment, the data processor (,) prefetches the vector into the first memory in response to a single data stream touch load (DST) instruction (,).

Data processing system for processing vector data and method therefor

A vector multiplication mechanism is provided that partitions vector multiplication operation into even and odd paths. In an odd path, odd data elements of first and second source vectors are selected, and multiplication operation is performed between each of the selected odd data elements of the first source vector and corresponding one of the selected odd data elements of the second source vector. In an even path, even data elements of the source vectors are selected, and multiplication operation is performed between each of the selected even data elements of the first source vector and corresponding one of the selected even data elements of the second source vector. Elements of resultant data of the two paths are merged together in a merge operation. The vector multiplication mechanism of the present invention preferably uses a single general-purpose register to store the resultant data of the odd path and the even path. In addition, computational overhead of the merge operation is amortized over a series of vector operations.

Method and apparatus for performing vector operation using separate multiplication on odd and even data elements of source vectors

The data processing system of the present invention loads three input operands, including two input vectors and a control vector, into vector registers and performs a permutation of the two input vectors as specified by the control vector, and further stores the result of the operation as the output operand in an output register. The control vector consists of sixteen indices, each uniquely identifying a single byte of input data in either of the input registers, and can be specified in the operational code or be the result of a computation previously performed within the vector registers. The specification of the control vector allows a vector-matrix operation to be performed on the input vectors by rearranging or replicating the input operand bytes in the bytes of the output register as a function of the control vector. This system provides a highly efficient register loading mechanism for data vectors misaligned in memory, and allows the computation of a serially dependent chain of binary functions within the vector registers.

Data processing system and method of permutation with replication within

A memory device (28) executes memory access operations of two or more storage locations concurrently. The memory device (28) is comprised of a plurality of memory bank decode logic circuits (30, 32, 56) and a plurality of memory banks (34, 52). Each of the decode logic circuits decodes a first information and control signal set to enable a first memory bank to begin and complete a memory access operation. Each memory bank is comprised of a plurality of latch circuits (39,40, 42, 50) to store a predetermined information and control signal set necessary to perform the memory access operation. A second control signal and information set may, therefore, enable a second memory bank within the memory device (28) to perform a second memory access operation concurrently in time with the first memory access operation.

Randomly accessible memory having time overlapping memory accesses

A data processing system has a bus meter, a memory capable of transferring operands requested by the bus master, and a cache for temporarily storing a selected number of the most recently transferred operands. If the memory provides an operand or a portion thereof which is insufficient in size or alignment to fill a complete entry in a line in the cache, the bus master automatically transfers additional operands adjacent in the memory to the requested operand sufficient to fill that entry.

Bus master which selectively attempts to fill complete entries in a

A data processing system having a bus master, a cache, and a memory which is capable of transferring operands in bursts in response to a burst request signal provided by the bus master. The bus master will provide the burst request signal to the memory in order to fill a line in the cache only if there are no valid entries in that cache line. If a requested operand spans two cache lines, the bus master will defer the burst request signal until the end of the transfer of that operand, so that only the second cache line will be burst filled.

Bus master having selective burst initiation

Bus master having selective burst deferral

A data processing system having a bus master and a memory which is capable of transferring operands in bursts of m in response to a burst request signal provided by the bus master, the operands being clustered modulo m about a selected access address provided by the bus master, where m is two (2) to the n power, n being an integer and characteristic of the memory. The bus master is adapted to automatically increment, modulo m, a selected set n of the bits of the access address as each operand in the burst is transferred, provided that the memory has indicated that the burst can be continued and less than m operands have been transferred.

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Austin, TX, United States of America

Hunter Ledbetter Scales, Iii