Vlsi Technology, Inc.

Philips Semiconductor, Inc.

Hunter B Brugge

Kin-Sang Lam

Milind Ganesh Weling

Kuang-Yeh Chang

David Howard Ziger

Landon B Vines

Felix H Fujishiro

Ramiro Solis

Chang-Ou Lee

Olivier F Laparra

Walter D Parmantie

Bijan Moslehi

Michela S Love

Disclosed are techniques to provide an integrated circuit, including the provision of improved integrated circuit isolation structures. The techniques include forming a number of trenches in an integrated circuit substrate to define a number of substrate regions that are to be electrically isolated from one another. A dielectric material is deposited in the trenches by exposure to a high density plasma having a first deposition-to-etch ratio. The high density plasma is adjusted to a second deposition-to-etch ratio greater than the first ratio to accumulate the dielectric material on the substrate after at least partially filling the trenches. A portion of the dielectric material is removed to planarize the workpiece. A number of components, such as insulated gate field effect transistors, may be subsequently formed in the substrate regions between the trenches.

Manufacture of an integrated circuit isolation structure

Chemical Mechanical Processing (CMP) is widely used for manufacturing semiconductors. CMP is very effective for planarizing geometry that are not widely isolated. One limiting aspect of CMP is that the deposition of the layer being planarized generally has an effective distance over which gaps can be filled. These gaps can fill with a residue that adversely effects the resultant semiconductor. A technique that inhibits the accumulation of residue deposits a sacrificial layer of material after deposition of a planarizing layer, but before CMP. This layer is selected so that it fills the gaps from the manufacturing process, but has little abrasive or solvent resistance. CMP is performed after the sacrificial layer is performed. However, since the gaps are filled, residues cannot collect. Then, after the CMP is performed, the sacrificial layer is removed by applying a solvent to the sacrificial layer. The choice of material for the sacrificial layer is also important. The sacrificial material must fill the gaps yet be very soluble for removal after the CMP processing is performed. A sacrificial layer having a low viscosity novalac polymer has excellent characteristics for a sacrificial layer. The sacrificial layer will ideally adequately fill spaces and have no abrasive resistance. The sacrificial layer must have adequate compressive strength and be slick enough, like glass, to prevent CMP residue from collecting on the fill areas.

System and method for residue entrapment utilizing a polish and sacrificial fill for semiconductor fabrication

The invention encompasses methods of forming pairs of transistor gates. In one aspect, the invention includes a method comprising: a) defining a first region and a second region of a substrate; the first region and second region comprising a first substrate surface and a second substrate surface, respectively; b) improving a lifetime of a low voltage tolerant transistor formed proximate the first substrate surface by cleaning the first substrate surface with a first mixture comprising hydrofluoric acid and hydrochloric acid; c) forming a first transistor gate over the first substrate region and incorporating the first transistor gate into the low-voltage tolerant transistor; and d) forming a second transistor gate over the second substrate region and incorporating the second transistor rate into a high-voltage tolerant transistor. In another aspect, the invention includes a method comprising: a) defining a first region and a second region of a substrate; the first region and second region comprising a first substrate surface and a second substrate surface, respectively; b) cleaning at least one of the first and second substrate surfaces with a first mixture comprising hydrofluoric acid and hydrochloric acid; c) after cleaning the at least one of the first and second substrate surfaces, forming a first oxide layer over the first and second substrate surfaces; d) removing the first oxide layer from over the first substrate surface while leaving the first oxide layer over the second substrate surface; and e) forming a second oxide layer over the first substrate surface.

Methods of forming pairs of transistors, and methods of forming pairs of

A sputter deposition system includes a mobile collimator. The collimator can be magnetically moved into and out of a position between a wafer and a target of material to be sputtered onto the wafer. In addition, magnets are used to levitate the collimator so that it can be removed without solid-solid friction, and the contamination it can cause. The magnets used for levitation are part of a control loop that maintains the orientation of the collimator parallel to the wafer. The system allows for a combination of good deposition step coverage and high fabrication throughput while minimizing opportunities for contamination and breakage that can occur when the wafer is transferred between chambers.

Sputter deposition with mobile collimator

A method of forming a metal interconnect structure for a CMOS integrated circuit provides for deposition of via metal prior to formation of an intermetal dielectric. After a submetal dielectric is deposited, lower metal and via metals are deposited. Gradient photolithography is used to define a via pattern and a lower metal pattern in a positive photoresist. After etching, the lower metal assumes the lower metal pattern and the via metal assumes the via pattern. A three-layer intermetal dielectric includes a spin-on glass sandwiched between two deposited silicon dioxide layers. The resulting structure is polished until at least some of the vias are exposed. Other vias can be exposed by via apertures that are define photolithographically. An upper metal layer is then deposited, filling the via apertures. The upper metal is then patterned to complete the interconnect structure. This method provides that via metal is insulated from spin-on glass moisture by the deposited oxide. Prior art problems with metal interconnect integrity due to misalignment, poor step coverage, and via poisoning are eliminated in some cases and reduced in others.

Integrated-circuit via formation using gradient photolithography

A titanium-tungsten barrier layer is sputtered after active areas of a CMOS structure are exposed. An ion implant through the barrier layer and into the active areas disrupts the boundaries between the barrier layer and the underlying active areas. The implant can involve argon or, alternatively, silicon. The resulting structure is annealed. A conductor layer of an aluminum-copper alloy is deposited. An antireflection coating of TiW is deposited. The three-layer structure is then photolithographically patterned to define contacts and local interconnects. The ion implant before anneal results in less contact resistance, which is particularly critical for the barrier layer boundary with positively doped active areas.

Integrated circuit contact barrier formation with ion implant

An improved barrier, and a method for forming such a barrier, between a semiconductor substrate and a metallized contact. A first metallic layer is deposited over the substrate and the contact well formed therein. The first metallic layer is then exposed to a gas to allow the gas to stuff the first metallic layer, thereby improving the barrier characteristics of the first metallic layer. A second metallic layer is deposited over the first stuffed metallic layer. A third metallic layer is then deposited over the second metallic layer. An anti-reflective fourth layer of metal is then deposited over the third metallic layer. The exposure of the first metallic layer to a gas and all of the metal layer deposition steps are performed in a low-pressure environment. Therefore, the present invention eliminates the need for time-consuming pressure breaks. As a result, the throughput of the present invention is substantially increased over prior art barrier formation processes. Also, as a result of subsequent processing steps required in the formation of semiconductor devices, the portions of the first metallic layer which are present outside of the contact well are removed. The remaining portion of the first metallic layer forms a self-aligned silicide within the contact well. Thus, the present invention eliminates the need for a separate etch step to remove unwanted portions of the first metallic layer, and also provides a self-aligned silicide without requiring a separate heating or sinter step.

Barrier enhancement at the salicide layer

The present invention concerns a magnet assembly for a sputtering chamber that allows for an even erosion of a target in the sputtering chamber so that atoms on the target are deposited on a wafer. This magnet assembly has a side magnet which is thinner than a center and ring magnet. This side magnet's centerplane is positioned above the centerplane of the other magnets. Additionally, this magnet assembly uses a center magnet in the range of substantially 350-450 Gauss and a side magnet of in the range of substantially 680-780 Gauss so that an asymmetrical magnetic field will be created which will cause an even erosion of the target and prevent re-deposition.

Magnet assembly for enhanced sputter target erosion

A sputter target assembly includes a main target plate formed of a refractory material, such as Ti/W, which provides a target surface which is bombarded by ions and from which is ejected refractory material for thin-film deposition. A removable center piece is formed of a refractory material and fits within a recess formed in the center region of the main target plate to provide a surface which is substantially coplanar with the target surface of the main target. The removable center piece is attached to the main target plate with a screw formed of a refractory material. The main target plate is bonded to a backing plate for cooling.

Growing community of inventors

San Antonio, TX, United States of America

Hunter B Brugge