Samsung Electronics Co., Ltd.

Hunkook Lee

Yoosang Hwang

Hui-Jung Kim

Bong-Soo Kim

Kiseok Lee

Jiyoung Kim

Hongsoo Kim

Seokhan Park

Keunnam Kim

Chul-Ho Kim

Cheolhong Kim

Juyeon Lee

Seunghak Park

Sihyun Kim

Yongju Jung

Jeehoon Hwang

Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

Semiconductor memory devices

A semiconductor memory device comprising a substrate including a cell region, first and second contact regions, and a bit peripheral circuit region disposed between the first and second contact regions. A first stack structure is disposed on the cell region and the first contact region. A second stack structure is disposed on the cell region and the second contact region. A peripheral transistor is disposed on the bit peripheral circuit region and is electrically connected to the first and second stack structures. Each of the first and second stack structures comprises semiconductor patterns vertically stacked on the cell region, and conductive lines having connection with the semiconductor patterns and extending along a first direction from the cell region onto corresponding first and second contact regions. The conductive lines have stepwise structures on the first and second contact regions.

Semiconductor memory device

A semiconductor memory device includes stacks on a substrate, each of the stacks including word lines stacked on the substrate and first and second string selection lines laterally spaced apart from each other, vertical pillars passing through the stacks, and first and second bit lines extending longitudinally in a first direction and alternatingly arranged in a second direction crossing the first direction. In a plan view, at least two adjacent ones of the first bit lines in the second direction and at least one of the second bit lines overlap each vertical pillar. A distance between a center of the vertical pillar and one of the first bit lines is different from that between the center of the vertical pillar and another of the first bit lines.

A semiconductor device is disclosed. The semiconductor device includes an electrode disposed on a substrate and a plurality of vertical patterns passing through the electrode. The vertical patterns include first vertical patterns arranged to form a rhombus and second vertical patterns arranged to form a non-regular trapezoid or a rhombus.

Semiconductor device

A semiconductor device may include an insulating layer provided in one body on a substrate, a first gate electrode and a second gate electrode disposed on the insulating layer, the first and second gate electrodes extending in a first direction parallel to a top surface of the substrate, a first channel structure penetrating the first gate electrode and the insulating layer so as to be connected to the substrate, a second channel structure penetrating the second gate electrode and the insulating layer so as to be connected to the substrate, and a contact penetrating the insulating layer between the first gate electrode and the second gate electrode. The contact may be connected to a common source region formed in the substrate, and the common source region may have a first conductivity type. Further, the first gate electrode and the second gate electrode may be spaced apart from each other in a second direction at the same level from the substrate, wherein the second direction intersects the first direction and is parallel to the top surface of the substrate.

Methods of preparing layouts for semiconductor devices and semiconductor devices fabricated using the layouts are provided. Preparing the layouts for semiconductor devices may include disposing assistant patterns near a main gate pattern that is provided on a weak active pattern. The weak active pattern may be, for example, an outermost one of active patterns and may be one expected to have an increased width during a fabrication process.

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Hwaseong-si, South Korea

Hunkook Lee