Nvidia Corporation

Hungse Cha

Richard L Schober, Jr

Eric Lyell Hill

Sean Jeffrey Treichler

Dennis K Ma

Robert J Hasslen

Robert Huang

Michael Hopgood

Abdulkadir Utku Diril

Vishal Mehta

John A Robinson

Feroze Karim

Srikanth Devarapalli

A method comprises performing a first pass test over a plurality of sets of equalization coefficients to filter the plurality of sets of equalization coefficients to produce one or more filtered sets of equalization coefficients. Each filtered set of equalization coefficients meets a first predetermined threshold. The method also comprises performing a second pass test over the one or more filtered sets of equalization coefficients to determine a final set of equalization coefficients that meets a second predetermined threshold. The second pass test produces more accurate results than the first pass test.

Multipass approach for performing channel equalization training

Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.

Cyclic redundancy check generation via distributed time multiplexed linear feedback shift registers

A power monitor for electronic devices, such as computer chips, is used to estimate the power consumption and to compare the estimated power consumption against the power budget. The estimated power consumption is based on activity signals from various functional blocks of the computer chip. The activity signals that are monitored correlate accurately to the total number of flip-flops that are active at a given time. If the estimated power consumption exceeds the power budget, the speed of the clock signals supplied to the computer chip is reduced.

Power estimation based on block activity

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Hungse Cha