Taiwan Semiconductor Manufacturing Comp. Ltd.

HungLung Lin

Wen-Ju Preet Yang

Chin-Chang Hsu

Ken-Hsien Hsieh

Ying-Yu Shen

Yi-Kan Cheng

Hsiao-Shu Chao

C R Hsu

Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict.

Conflict detection for self-aligned multiple patterning compliance

Among other things, techniques for balancing mask loading are provided for herein. In some embodiments, one or more windows are defined within a layout. Based upon polygons comprised within respective windows, a localized mask loading is computed for the layout. In some embodiments, a global mask loading is also computed for the layout. Using the localized mask loading and the global mask loading, if computed, a loading effect of a plurality of mask pattern schemes is evaluated to identify a mask pattern scheme having a desired loading effect.

Balancing mask loading

Among other things, one or more techniques for balancing mask loading are provided herein. In some embodiments, a dummy mask assignment is assigned to a dummy within a mask layout based on an area of a polygon within the mask layout. In some embodiments, the dummy mask comprising the dummy mask assignment is inserted in the mask layout. In some embodiments, a window is created such that dummies within the window receive dummy mask assignments. In some embodiments, a halo is created such that the area of the polygon is determined based on the halo. Additionally, in some examples, the window and halo are shifted around the mask layout. In this manner, balanced mask loading is provided, thus enhancing a yield associated with the mask layout, for example.

The present disclosure relates to a method and apparatus for identifying pre-coloring violations and for providing hints and/or warnings to a designer to eliminate the pre-coloring violations. In some embodiments, the method is performed by identifying G0-spaces within a double patterning technology (DPT) layer, of an integrated chip (IC) layout, having a plurality of pre-colored shapes. Violation paths extending between the pre-colored shapes are identified based upon the G0-spaces. Good paths (i.e., paths that will not cause a violation) and bad paths (i.e., paths that will cause a violation) between the pre-colored shapes are also identified. Hints and/or warnings are generated based upon the identified good and bad paths, wherein the hints and/or warnings provide guidance to eliminate the violation paths and develop a violation free IC layout.

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Hsinchu, Taiwan

HungLung Lin