Marvell International Limited

Flc Technology Group, Inc.

Marvellworld Trade Ltd.

Hunglin Hsu

Viney Gautam

Yicheng Guo

Sehat Sutardja

Fan Yang

Chia-Hung Chien

Warren Menezes

Rong Xu

Xiaojue Zeng

Eitan Joshua

Michael Weiner

Oren Shafrir

Nadav Klein

Junhua Xu

Cheng Chung Wang

Bo Hu

To avoid hash table collisions, such as in response to sequential addresses, a hash module is provided that includes a first multiplexer that, responsive to a control signal, outputs received data on one of two or more scramblers. The scramblers are configured to selectively receive the selected data output from the first multiplexer and perform a scrambler operation on the selected data to generate scrambled data. A second multiplexer outputs the scrambled data to a first hash module configured to performs a hash function on the scrambled data to generate a hash value. A second hash module, responsive to a collision occurring in the first hash module, perform a hash function on the scrambled data received from the first hash module. The use of a scrambler reduces collisions in the hash module outputs over time and multiple scramblers may be used to further reduce collisions.

Hash function with pre-scrambler

A system and method for caching memory request verification data comprising a memory request generator configured to generate a memory request designating requested data and memory request verification data. A bus is configured to carry the memory request from the memory request generator to a cache memory that stores verification data, and upon receiving the memory request is configured to: retrieve stored verification data from the cache memory, compare the stored verification data to the memory request verification data, and responsive to a match between the stored verification data to the memory request verification data, designate a memory request validation. Also part of the system is a memory controller configured to, responsive to a memory request validation, retrieve data specified in the memory request from a main memory and provide the data to the memory request generator over the bus. A main memory configured to store the requested data.

Method and apparatus for caching MTE and/or ECC data

Systems and methods described herein provide for communicating an addressable request from cache circuitry to a cache memory. The addressable request is received at a hardware bridge coupled to the cache circuitry and is directed to the cache memory, wherein the cache memory includes a direct memory access (DMA) memory and a programmable input/output (PIO) memory operable within a same address space of the cache circuitry. A service command associated with the addressable request is sent from the hardware bridge to a microcontroller. In response to receiving the service command, the microcontroller activates the PIO memory by: 1) transferring write data from an on-die memory to the PIO memory when the service command is a write command, and 2) transferring read data from the PIO memory to the on-die memory when the service command is a read command.

Systems and methods for communicating addressable requests to a programmable input/output memory over a hardware bridge

A Dynamic Random Access Memory (DRAM) controller includes a memory interface and a processor. The memory interface is configured to communicate with a DRAM including one or more memory banks. The processor is configured to receive Input/Output (I/O) commands, each I/O command addressing a respective memory bank and a respective row within the memory bank to be accessed in the DRAM, to further receive one or more indications, indicative of likelihoods that a subsequent I/O command will address a same row in a same memory bank as a previous I/O command, to adaptively set, based on the indications, a policy of deactivating rows of the DRAM, and to execute the I/O commands in the DRAM in accordance with the policy.

DRAM controller with adaptive precharge policy

An apparatus comprises an event memory to store one or more events, and a prefetch circuit. The prefetch circuit a) detects a current stride between a first address and a second address, b) detects a stride break using the current stride and a stride of a first dimension, and c) stores a first event in the event memory when the stride break is detected. The first event includes i) an event address corresponding to the first address, and ii) a stride corresponding to the current stride. A method for generating a prefetch address comprises detecting, by a prefetch circuit, a first stride break between a first address of a stream and a second address of the stream, storing, in the prefetch circuit, a first event corresponding to the first stride break; and generating, by the prefetch circuit, an output prefetch address using the stored first event.

Multi-dimensional prefetching

A circuit has an address generation circuit to produce a virtual address (VA) and an index signal and a multi-way cache circuit. The cache circuit has a plurality of Random Access Memory (RAM) groups and a hash function circuit to generate a hash output from the VA. Each RAM group includes RAMs respectively corresponding to the ways. The cache circuit selects, using the hash output, a selected RAM group of the RAM groups, and performs, using the index signal as an address, an operation using one or more RAMs of the selected RAM group. Controlling a multi-way cache circuit comprises determining a hash value using a VA, selecting, using the hash value, a RAM group from a plurality of RAM groups, and performing an operation by using one or more RAMs of the selected RAM group. The RAMs of each RAM group respectively correspond to the ways.

Data caching circuit and method

In aspects of determining memory access patterns for cache prefetch in an out-of-order processor, data is maintained in a cache when copied from system memory of a computing device, and load data instructions are processed to access the cache data. The load data instructions include incremental load data instructions and non-incremental load data instructions that access the data from contiguous memory addresses. The data is prefetched ahead of processing the load data instructions, where prefetch requests are initiated based on the load data instructions. A stride is calculated as the distance between the incremental load data instructions. Further, the stride can be corrected for the non-incremental load data instructions to correlate with the calculated stride. The corrected stride represents the data as a sequential data stream having a fixed stride, and prefetching the data appears sequential for both the incremental and non-incremental load data instructions.

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Cupertino, CA, United States of America

Hunglin Hsu