Qualcomm Incorporated

Siliconware Precision Industries Co., Ltd.

Hung-Yuan Hsu

Dongming He

Sui-An Kao

Yangyang Sun

Lily Zhao

Wei Wang

Wei Hu

Yujen Chen

A thermal compression flip chip (TCFC) bump may be used for high performance products that benefit from a fine pitch. In one example, a new TCFC bump structure adds a metal pad underneath the TCFC copper pillar bump to cover the exposed aluminum bump pad. This new structure prevents the pad from corroding and reduces mechanical stress to the pad and underlying silicon dielectric layers enabling better quality and reliability and further bump size reduction. For example, a flip chip connection may include a substrate; a metal pad on a contact side of the substrate and a first passivation layer on the contact side of the substrate to protect the metal pad from corrosion.

Thermal compression flip chip bump for high performance and fine pitch

A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity. The plurality of solder interconnects comprises a first solder interconnect located in the first cavity of the first pillar interconnect. A planar cross section that extends through the first cavity of the first pillar interconnect may comprise an O shape. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width; and a second pillar interconnect portion comprising a second width that is different than the first width.

Integrated device comprising pillar interconnect with cavity

A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.

Chip structure having redistribution layer

Chip structure having redistribution layer and fabrication method thereof

Growing community of inventors

Taichung, Taiwan

Hung-Yuan Hsu